ACE24AC04.08.16

Two-wire Serial EEPROM

VER 1.2

6

bit. After receiving the stop bit, the EEPROM will go into a self-timed programming mode during

finish and the EEPROM device will return to the standby mode.

B.

Page Write

A page write is similar to a byte write with the exception that one to sixteen bytes can be

programmed along the same page or memory row. All ACE24AC04.08.16 are organized to have 16

bytes per memory row or page.

With the same write command as the byte write, the micro-controller does not issue a stop bit after

sending the 1

cycle. Instead it sends out a second 8-bit data word, with the EEPROM acknowledging at the 36

th

cycle. This data sending and EEPROM acknowledging cycle repeats until the micro-controller sends

a stop bit after the n × 9

devices will return to the standby mode.

The least significant 4 bits of the word address (column address) increments internally by one after

receiving each data word. The rest of the word address bits (row address) do not change internally,

but pointing to a specific memory row or page to be programmed. The first page write data word can

be of any column address. Up to 16 data words can be loaded into a page.

If more then 16 data

words are loaded, the 17

th

data word will be loaded to the 1

st

data word column address. The 18

th

data word will be loaded to the 2

nd

data word column address and so on.

In other word, data word

address (column address) will “roll” over the previously loaded data.

C.

Acknowledge polling may be used to poll the programming status during a self-timed internal

programming. By issuing a valid read or write address command, the EEPROM will not acknowledge

at the 9

programming completes and the chip has returned to the standby mode, the device will return a valid

acknowledge signal at the 9

Read Operations

The read command is similar to the write command except the 8th read/write bit in address word is set to

“1”. The three read operation modes are described as follows:

(A)

Current Address Read

The EEPROM internal address word counter maintains the last read or write address plus one if the

power supply to the device has not been cut off. To initiate a current address read operation, the

micro-controller issues a start bit and a valid device address word with the read/write bit (8th) set

to

“1”. The EEPROM will response with an acknowledge signal on the 9th serial clock cycle. An

8-bit data word will then be serially clocked out. The internal address word counter will then