R5F10RFAA datasheet(39/136 Pages) RENESAS

39 / 136 page

RL78/L12

2. ELECTRICAL SPECIFICATIONS (A, G: TA = -40 to +85

°C)

R01DS0157EJ0210 Rev.2.10

Sep 30, 2016

Page 39 of 131

2.5 Peripheral Functions Characteristics

AC Timing Test Points

VIH/VOH

VIL/VOL

Test points

VIH/VOH

VIL/VOL

2.5.1 Serial array unit

(1) During communication at same potential (UART mode)

(TA =

−40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Unit

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Transfer rate

Note 1

2.4 V

≤ EVDD = VDD ≤ 5.5 V

fMCK/6

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK

Note 2

4.0

1.3

0.6

Mbps

1.8 V

≤ EVDD = VDD ≤ 5.5 V

fMCK/6

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK

Note 2

1.3

0.6

Mbps

1.6 V

≤ EVDD = VDD ≤ 5.5 V

fMCK/6

bps

Theoretical value of the

maximum transfer rate

fMCK = fCLK

Note 2

0.6

Mbps

Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.

2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode:

24 MHz (2.7 V

≤ VDD ≤ 5.5 V)

16 MHz (2.4 V

≤ VDD ≤ 5.5 V)

LS (low-speed main) mode:

8 MHz (1.8 V

≤ VDD ≤ 5.5 V)

LV (low-voltage main) mode:

4 MHz (1.6 V

≤ VDD ≤ 5.5 V)

Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using

port input mode register g (PIMg) and port output mode register g (POMg).

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