PLQP0048KB-B datasheet(69/98 Pages) RENESAS

69 / 98 page

R01DS0248EJ0110 Rev.1.10

Page 69 of 98

Jan 13, 2016

RX23T Group

5. Electrical Characteristics

Note 1. tPcyc: PCLK cycle

Note 2. Cb is the total capacitance of the bus lines.

Figure 5.34

I/O Port Input Timing

Figure 5.35

MTU3 Input/Output Timing

Table 5.27

Timing of On-Chip Peripheral Modules (5)

Conditions: VCC = 2.7 V to 5.5 V, AVCC0 = VREFH0 = VCC to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C

Item

Symbol

Min.*2

Max.

Unit

Test

Conditions

Simple I2C

(Standard mode)

SDA rise time

tSr

—

1000

Figure 5.47

SDA fall time

tSf

—

300

SDA spike pulse removal time

tSP

04 × tpcyc*1

Data setup time

tSDAS

250

—

Data hold time

tSDAH

0—

SCL, SDA capacitive load

—

400

Simple I2C

(Fast mode)

SDA rise time

tSr

—

300

Figure 5.47

SDA fall time

tSf

—

300

SDA spike pulse removal time

tSP

04 × tpcyc*1

Data setup time

tSDAS

100

—

Data hold time

tSDAH

0—

SCL, SDA capacitive load

—

400

Port

PCLK

tPRW

Output

compare output

Input capture

input

PCLKA

tTICW

PLQP0048KB-B Datasheet(PDF) 69 Page - Renesas Technology Corp

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