MC33099DWSLASHR2 datasheet(10/20 Pages) MOTOROLA

10 / 20 page

33099

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

waveform has a duty cycle regulation output frequency of about

395 Hz (fdc) defined by an 8-bit division of an internal 101 kHz

oscillator clock frequency (fosc). The GATE voltage at the GATE

terminal is due to a charge pump GATE voltage (Vg) generated

by voltage multiplication using an internal charge pump voltage

regulator. The high GATE-to-source voltage applied to the

external MOSFET during the ON cycle of the PWM waveform

minimizes a low drain-to-source ON resistance (RDS(ON)) and

associated drain-to-source voltage Vd(SAT) to maximize the field

current while minimizing the associated power dissipation in the

MOSFET.

A unique feature of the 33099 is the combinational use of

analog and digital duty cycle controllers to provide a Load

Response Control (LRC) duty cycle function when rotor

frequency fph is less than frequency f2. A classic analog duty

cycle function is provided at the GATE output when frequency

fph is greater than frequency f2. During the LRC mode when f1

< fph < f2, a sudden decrease in the system voltage due to a

sudden increase in system load current will cause the analog

duty cycle to rapidly increase to as great as 100%. However,

the LRC circuitry causes the digital duty cycle to increase to

100% at a controlled predetermined LRC rate and overrides the

analog duty cycle. Thus the alternator response time is

decreased in the LRC mode and prevents the alternator from

placing a sudden high torque load on the automobile engine

during this slow RPM mode. This can occur when a high current

accessory is switched on to the 12 V system, producing a

sudden drop in system voltage. When frequency fph is greater

than frequency f2, the slow LRC response is not in effect and

the analog duty cycle controller controls the PWM voltage

waveform applied to the external MOSFET to regulate the

system voltage. By selectively coupling the LRC1 and LRC2

terminals to ground or leaving them open, the user can program

four different LRC rates (Rlrc1-Rlrc4) from 9.37%/sec to 37.4%/

sec. During an initial ignition ON and engine start-up, the LRC

rate is also in effect to minimize alternator torque loading on the

engine during start, even when a Wide Open Throttle (WOT)

condition (fph >f2) occurs.

An internal N-Channel MOSFET is provided on the IC to

directly drive lamp current as a fault indicator. The fault lamp is

connected between the low side of the ignition switch and the

LAMP DRAIN terminal of the IC. A fault is indicated during an

undervoltage battery condition when frequency fph is greater

than frequency f2, during an overvoltage battery condition, and

when frequency fph is less than frequency f1. Frequency fph < f1

when an insufficient alternator output voltage results or a slow

or non-rotating rotor occurs due to a slipping or broken belt. An

external LAMP GATE terminal is also provided for the internal

lamp driver to allow the user to override the internal IC fault logic

and externally drive the internal lamp drive MOSFET.

When a loose wire or battery terminal corrosion causes the

Remote voltage to decrease but is not a Remote Open

condition, the system voltage will increase, causing an

overvoltage Lamp fault indication, and is regulated at a

secondary value of about 18.5 V.

During a system load dump condition, load dump protection

circuitry prevents GATE-to-source drive to the external

MOSFET and to the internal lamp drive MOSFET. This ensures

that neither the field current nor the lamp current is activated

during load dump conditions. A drain-to-GATE voltage clamp is

also provided for the internal lamp driver for further protection of

this driver during load dump.

An ignition terminal (IGN) is provided to activate the regulator

from the standby mode into a normal operating mode when the

ignition switch is ON and an ignition voltage (Vign) is greater

than a power up/down ignition threshold voltage (VTign). When

the ignition switch is OFF, voltage Vign is less than voltage

VTign, and the regulator is switched into a low current standby

mode, when frequency fph < f1. The IGN terminal can either be

coupled to the low side of the ignition switch or to the low side

of the lamp. When the IGN terminal is connected to the low side

of the lamp, the lamp must be shunted by a resistor to ensure

that ignition ON is sensed, even with an OPEN lamp fault

condition. When the lamp in ON, lamp current is polled OFF

periodically at an ignition polling frequency in order for the IGN

terminal to periodically sense that the ignition voltage is high

even though the lamp is ON. An ignition input pull-down current

(Iign) is provided to pull voltage Vign to ground when the IGN

terminal is OPEN or terminated on a high resistance.

Two ground terminals are provided by the 33099 to separate

sensitive analog circuit ground (AGND) from noisy digital and

high-current ground (GND).

Alternator Regulator Biasing and Power Up/Down

The biasing of the regulator is derived from the BAT terminal

voltage Vbat. In the normal operating mode when the ignition

switch is ON and voltage Vign is greater than VTign (about

1.25 V), a 5.0 V VDD voltage regulator biases the IC logic and

provides bias to a bandgap shunt voltage regulator. The

bandgap regulator maintains a reference voltage (Vref) of

approximately 2.0 V with an internal negative temperature

coefficient (-TC) as well as a 1.25 V Zero Temperature

Coefficient (OTC) reference voltage. Additional bias currents

and reference voltages, including a charge pump GATE voltage

Vg, are also generated from voltage Vbat. The typically ignition

ON drain current (IQ1(on)) is about 6.5 mA at 25°C. When the

ignition switch is OFF and voltage Vign is less than VTign, the

regulator is in a low current standby mode, having a standby

drain current of about 0.7 mA (IQ1(off) ) at 25°C. During the

sleep mode, some internal voltage regulators and bias currents

are either terminated or minimized. However, the VDD regulator

and the bandgap voltage regulator continue to maintain

voltages VDD for the logic, the 2.0 V Vref, and the 1.25 V

reference voltage. In addition, all logic is reset in the standby

mode.

After switching the ignition switch to the ON position, voltage

Vign will exceed voltage VTign, causing comparator Cign to

switch states, providing an ignition-ON signal to the Ignition

Delay circuit. After an Ignition start Delay Time of 500 ms, the

Ignition Delay circuit activates additional current for the VDD

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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