MC33099DWSLASHR2 datasheet(13/20 Pages) MOTOROLA

13 / 20 page

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33099

engine start, the LRC response is in effect, independent of

frequency fph, until system voltage is regulating at voltage Vset.

The digital duty cycle generator receives the 4 MSBs from

the 8-bit counter as input and generates 11 discrete digital duty

cycles on 11 output lines. The frequency of each duty cycle

waveform is about 395 Hz (fmsb), which results from the MSB

of the 8-bit division of the 101 kHz OSC clock frequency. The

minimum duty cycle on the first output line is 31.25% and the

maximum duty cycle on the eleventh output line is 93.75%. The

duty cycle difference between each incremental duty cycle is

6.25%. All 11 duty cycle generator output lines are coupled as

data inputs to the MUX.

Normally the programmable divider Np divides frequency

fmsb by a counter divide ratio N and applies the fmsb/N

frequency as input to the U/D counter. Divide ratio N can be pre-

selected by the user for four different divide ratios by switching

a combination of the LRC1 and LRC2 normally open terminals

to ground. An LRC input current (Ilrc) from each LRC terminal to

ground is about 45 µA. The phase frequency fph and an up/

down (u/d) state on a u/d line from the up/down control switch

determines ratio N. In the LRC mode when fph <f2, a high, or

up, state on the u/d line causes divider Np to output a frequency

of fmsb/N, or 395 Hz/N. The LRC1 and LRC2 terminal

combinations produce N divide ratios of 66, 132, 198, and 264.

When the u/d line is in the down, or low, state, divider Np

provides a divide ratio of fmsb/4, or 395 Hz/4. When fph >f2, the

output frequency of divider Np is always fmsb/4 = 395 Hz/4,

independent of the state of the u/d input line.

The u/d line from the up/down control switch determines the

direction of the count as well as the divide ratio N. For an up

state on the u/d line, the output of the 4-bit U/D counter

increments up at a rate of 5.98 Hz (count change every 167 ms)

for N=66, 2.99 Hz (count change every 334 ms) for N=132,

1.99 Hz (count change every 502 ms) for N = 198, or 1.496 Hz

(count change every 671 ms) for N = 264. For a down state on

the u/d line, the output of the 4-bit U/D counter decrements at a

rate of about 99 Hz (count decrement about every 10 ms). The

4-bit output lines of the up/down counter are coupled as control

inputs of the MUX.

The MUX couples one of the 11 digital duty cycle input lines

to the MUX output dependent upon the 4-bit control inputs from

the U/D counter. When the MUX control input count is 0, the first

31.25% digital duty cycle is selected and provided at the MUX

output. When the control input count is 10, the eleventh 93.75%

digital duty cycle is selected at output of the MUX. A MUX

control input of 11 produces a 100% duty cycle at the MUX

output. Thus each of the MUX input lines is selected and

provided at the MUX output and incremented to the next line at

a rate dependent on the rate the MUX control inputs increment.

For an up state on the u/d line, the digital duty cycle at the

output of the MUX will increment from 31.24% to 100% in

11 steps at a rate from 167 ms/step (or a fourth LRC rate (Rlrc4)

of 37.42%/sec) to 671 ms/step (or a first LRC rate (Rlrc1) of

9.31%/sec) dependent on the LRC1 and LRC2 terminal

terminations. For a down state on the u/d line, the digital duty

cycle will count down at a rate of about 10 ms/step change.

The A/D duty cycle comparator and tracking circuit receives

the analog duty cycle from comparator Cdc and the digital duty

cycle from the MUX output. The A/D duty cycle comparator

provides a high, or up (u), output when the analog duty cycle is

greater than the digital duty cycle, and a low, or down (d), output

when the analog duty cycle is less than the digital duty cycle.

In the LRC mode when frequency f1 <fph <f2, the up/down

control switch enables the u/d output of the A/D duty cycle

comparator to be coupled to the u/d line. In the steady state, the

A/D duty cycle comparator will provide an u/d input to the U/D

counter and Np divider to increase or decrease the digital duty

cycle to track the analog duty cycle. If the analog duty cycle

increases to a value greater than the digital duty cycle at a rate

that is greater than the selected LRC digital duty cycle rate, the

A/D duty cycle comparator will output an up signal on the

u/d line to cause the digital duty cycle to increase to the analog

duty cycle at the selected LRC digital duty cycle rate. If the

analog duty cycle decreases to a value less than the digital duty

cycle, the A/D duty cycle comparator will output a down signal

on the u/d line to cause the digital duty cycle to decrease to the

analog duty cycle at a fixed rate of about 10 ms/step. For an

analog duty cycle less than 31.25%, the down count at the

output of the U/D counter will remain at 0 and the digital duty

cycle will remain at 31.25%.

If frequency fph is less than frequency f1 (fph < f1), then the

up/down control switch will provide a down signal on the u/d line

independent of the duty cycle comparator u/d output. The

resulting down count of 0 to the MUX control input for fph <f1

will cause the digital duty cycle to be constant at 31.25% and

provides a divide ratio of fmsb/4 as the input frequency to the

U/D counter.

When approximately 5.0 V is applied to the LRC TEST

terminal, divider Np utilizes the fosc/16 frequency as input to the

divider instead of the normal fosc/256 frequency. As a result,

the LRC function is accelerated by a factor of 16, which allows

the testing of all LRC associated rates to be accelerated by a

factor of 16. During normal LRC operation, the LRC terminal is

in a low ground state, having an internal 10 kΩ pull-down

resistor.

The duty cycle output of the AND3 GATE reflects the

minimum duty cycle at the AND3 GATE inputs. Thus when the

analog duty cycle exceeds the digital duty cycle, the digital duty

cycle becomes the controlling duty cycle at the AND3 GATE

output. When the analog duty cycle is less than the digital duty

cycle, the analog duty cycle becomes the controlling duty cycle

at the AND3 GATE output. Thus in the LRC mode when

f1 <fph <f2, an increasing step response in the analog duty

cycle from 0% to 100% will cause the duty cycle at the output of

the AND3 GATE to increase rapidly from 0% to 31.25% and

then increase slowly at the LRC rate from 31.25% to 100%. If

the analog duty cycle provides a step increase from a duty cycle

greater than 31.25%, then the resulting LRC duty cycle

increase from the initial analog duty cycle at the output of the

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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