PIC12CE67X datasheet(27/116 Pages) MICROCHIP

27 / 116 page

Preliminary

DS40181B-page 27

PIC12CE67X

6.0

EEPROM PERIPHERAL

OPERATION

The PIC12CE673 and PIC12CE674 each have 16

bytes of EEPROM data memory. The EEPROM mem-

ory has an endurance of 1,000,000 erase/write cycles

and a data retention of greater than 40 years. The

EEPROM data memory supports a bi-directional 2-wire

bus and data transmission protocol. These two-wires

are serial data (SDA) and serial clock (SCL), that are

mapped to bit6 and bit7, respectively, of the GPIO reg-

ister (SFR 06h). Unlike the GP0-GP5 that are con-

nected to the I/O pins, SDA and SCL are only

connected to the internal EEPROM peripheral. For

most applications, all that is required is calls to the fol-

lowing functions:

; Byte_Write: Byte write routine

;

Inputs: EEPROM Address

EEADDR

;

EEPROM Data

EEDATA

;

Outputs:

Return 01 in W if OK, else

return 00 in W

;

; Read_Current: Read EEPROM at address

currently held by EE device.

;

Inputs: NONE

;

Outputs:

EEPROM Data

EEDATA

;

Return 01 in W if OK, else

return 00 in W

;

; Read_Random: Read EEPROM byte at supplied

address

;

Inputs: EEPROM Address

EEADDR

;

Outputs:

EEPROM Data

EEDATA

;

Return 01 in W if OK,

else return 00 in W

The code for these functions is available on our web

site (www.microchip.com). The code will be accessed

by either including the source code FL67XINC.ASM or

by linking FLASH67X.ASM. FLASH62.IMC provides

external deﬁnition to the calling program.

6.0.1

SERIAL DATA

SDA is a bi-directional pin used to transfer addresses

and data into and data out of the device.

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

6.0.2

SERIAL CLOCK

This SCL input is used to synchronize the data transfer

from and to the EEPROM.

6.1

BUS CHARACTERISTICS

The following bus protocol is to be used with the

EEPROM data memory. In this section, the term “pro-

cessor” is used to denote the portion of the

PIC12CE67X that interfaces to the EEPROM via soft-

ware.

• Data transfer may be initiated only when the bus

is not busy.

During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data

line while the clock line is HIGH will be interpreted as a

START or STOP condition.

Accordingly, the following bus conditions have been

deﬁned (Figure 6-1).

6.1.1

BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

6.1.2

START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

6.1.3

STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

6.1.4

DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the processor

device and is theoretically unlimited.

6.1.5

ACKNOWLEDGE

The EEPROM, when addressed, will generate an

acknowledge after the reception of each byte. The pro-

cessor must generate an extra clock pulse which is

associated with this acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse.

course, setup and hold times must be taken into

account. The processor must signal an end of data to

the EEPROM by not generating an acknowledge bit on

the last byte that has been clocked out of the EEPROM.

In this case, the EEPROM must leave the data line

HIGH to enable the processor to generate the STOP

condition (Figure 6-2).

Note:

Acknowledge bits are not generated if an

internal programming cycle is in progress.

PIC12CE67X Datasheet(PDF) 27 Page - Microchip Technology

PIC12CE67X Datasheet(HTML) 27 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL