CY23FS04
Document #: 38-07304 Rev. *B
Page 3 of 12
In this mode, should the reference frequency fail (i.e. stop or
disappear), the DCXO maintains its last setting and a flag
signal (FAIL#/SAFE) is set to indicate failure of the reference
clock.
The CY23FS04 provides 2 select bits, S1 through S2 to control
the reference to crystal frequency ratio. The DCXO is internally
tuned to the phase and frequency of the external reference
only when the reference frequency divided by this ratio is
within the DCXO capture range. If the frequency is out of
range, a flag will be set on the FAIL#/SAFE pin notifying the
system that the selected reference is not valid. If the reference
moves in range, then the flag will be cleared, indicating to the
system that the selected reference is valid.
Table 2. FailSafe Timing Table
Parameter
Description
Conditions
Min.
Max.
Unit
tFSL
Fail#/Safe Assert Delay
Measured at 80% to 20%, Load = 15 pF
See Figure 2
ns
tFSH
Fail#/Safe De-assert Delay
Measured at 80% to 20%, Load = 15 pF
See Figure 2
ns
n = F RE F
F
XT A L
=4 ( in abo v e ex am ple )
t
FS L ( m a x ) = 2
t
RE F x n
(
)
+
25ns
t
FS H ( m in ) = 1 2
t
RE F x n
(
)
+
25 ns
Figure 2. Fail#/Safe Timing Formula
Reference + 300 ppm
Reference - 300 ppm
Reference
Output + 300 ppm
Output - 300 ppm
Output
Fail#/Safe
t
FSH
Reference Off
t
FSL
Time
Figure 3. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range
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