Pin Descriptions

Pin

Name

LLP Pin

Number

LQFP

Pin

Number

I/O, Type

Description

DIFFERENTIAL INPUTS COMMON TO ALL MUXES

IN0+

IN0−

9

10

9

10

I, LVDS

Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

IN1+

IN1−

12

13

13

14

I, LVDS

Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or

LVPECL compatible.

SWITCHED DIFFERENTIAL OUTPUTS

OUT0+

OUT0−

27

26

32

31

O, LVDS

OUT1+

OUT1−

24

23

28

27

O, LVDS

DIGITAL CONTROL INTERFACE

SEL0,

SEL1

6

5

7

6

I, LVTTL

Select Control Inputs

EN0,

EN1

7

15

8

17

I, LVTTL

Output Enable Inputs

PEM00,

PEM01

4

3

4

3

I, LVTTL

Channel 0 Output Pre-emphasis Control Inputs

PEM10,

PEM11

2

1

2

1

I, LVTTL

Channel 1 Output Pre-emphasis Control Inputs

TDI

19

22

I, LVTTL

Test Data Input to support IEEE 1149.1 features

TDO

20

23

O, LVTTL

Test Data Output to support IEEE 1149.1 features

TMS

18

21

I, LVTTL

Test Mode Select to support IEEE 1149.1 features

TCK

17

19

I, LVTTL

Test Clock to support IEEE 1149.1 features

TRST

21

24

I, LVTTL

Test Reset to support IEEE 1149.1 features

N/C

8, 28

Not Connected

POWER

V

DD

11, 14,

16, 22,

25

12, 16,

18, 25,

29

I, Power

V

connected from V

GND

(Note 1) 5, 11, 15,

20, 26,

30

Ground reference to LVDS and CMOS circuitry.

For the LLP package, the DAP is used as the primary GND connection to the

device. The DAP is the exposed metal contact at the bottom of the LLP-28

package. It should be connected to the ground plane with at least 4 vias for

optimal AC and thermal performance.

Note 1: Note that for the LLP package GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package.

Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90CP02 device have been optimized for

point-to-point backplane and cable applications.

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