AD2S1210CSTZ datasheet(32/37 Pages) AD

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AD2S1210

Rev. A | Page 31 of 36

INCREMENTAL ENCODER OUTPUTS

The A, B, and NM incremental encoder emulation outputs are

free running and are valid if the resolver format input signals

applied to the converter are valid.

The AD2S1210 can be configured to emulate a 256-line, a

1024-line, a 4096-line, or a 16,384-line encoder. For example,

if the AD2S1210 is configured for 12-bit resolution, one revolu-

tion produces 1024 A and B pulses. Pulse A leads Pulse B for

increasing angular rotation (that is, clockwise direction).

The resolution of the encoder emulation outputs of the AD2S1210

is generally configured to match the resolution of the digital output.

However, the encoder emulation outputs of the AD2S1210 can also

be configured to have a lower resolution than the digital outputs.

For example, if the AD2S1210 is configured for 16-bit resolu-

tion, then the encoder emulation outputs can also be configured

for 14-bit, 12-bit, or 10-bit resolution. However, the resolution

of the encoder emulation outputs cannot be higher than the

resolution of the digital output. If the AD2S1210 is configured

such that the resolution of the encoder emulation outputs is

higher than the resolution of the digital outputs, the AD2S1210

internally overrides this configuration. In this event, the resolu-

tion of the encoder outputs is set to match the resolution of the

digital outputs. The resolution of the encoder emulation outputs

can be programmed by writing to Bit D3 and Bit D2 of the

control register.

The north marker pulse is generated as the absolute angular

position passes through zero. The north marker pulse width

is set internally for 90° and is defined relative to the A cycle.

Figure 36 details the relationship between A, B, and NM.

Figure 36. A, B, and NM Timing for Clockwise Rotation

The inclusion of A and B outputs allows the AD2S1210 with

resolver solution to replace optical encoders directly without

the need to change or upgrade existing application software.

SUPPLY SEQUENCING AND RESET

The AD2S1210 requires an external reset signal to hold the

RESET input low until VDD is within the specified operating

range of 4.5 V to 5.5 V.

The RESET pin must be held low for a minimum of 10 μs after

VDD is within the specified range (shown as tRST in

Applying a

Figure 37

RESET signal to the AD2S1210 initializes the output

position to a value of 0x000 (degrees output through the parallel,

serial, and encoder interfaces) and causes LOS to be indicated

(LOT and DOS pins pulled low), as shown in

Figure 37

Failure to apply the correct power-up/reset sequence may result

in an incorrect position indication.

After a rising edge on the RESET input, the device must be allowed

at least tTRACK ms (see

) for the internal circuitry to stabil-

ize and the tracking loop to settle to the step change of the input

position. For the duration of tTRACK fault indications may occur

on the LOT and DOS pins due to the step response caused by

the

Figure 37

RESET. The duration of tTRACK is dependent on the converter

resolution as outlined in

. After tTRACK, the fault register

should be read and cleared as outlined in the

section. The time required to read and clear the fault

speed of the DSP/microprocessor used in the application. (Note

that if position data is acquired via the encoder outputs, these

can be monitored during tTRACK.)

Table 27

Clearing the Fault

Table 27. tTRACK vs. Resolution (fCLKIN = 8.192 MHz)

Resolution (Bits)

tTRACK (ms)

VDD

DOS

LOT

SAMPLE

RESET

VALID

OUTPUT

DATA

tRST

tTRACK

tFAULT

4.75V

Figure 37. Power Supply Sequencing and Reset

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