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ATPL00B Datasheet(PDF) 56 Page - ATMEL Corporation |
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ATPL00B Datasheet(HTML) 56 Page - ATMEL Corporation |
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56 / 152 page  Atmel ATPL00B [datasheet] 43028A-ATPL - 9/12 56 When timer 2 is configured as a timer and in baud rate generator mode, do not read or write the TH2 or TL2 registers. The timer is being incremented every state time, and the results of a read or write may not be accurate. In addition, user shall read, but not write to, the RCAP2 registers; a write may overlap a reload and cause write and/or reload errors. Table 5-3 lists commonly used baud rates and shows how they are generated by timer 2. Table 5-3. Timer 2 generated baud rates with a 11.0592MHz oscillator Baud rate T2PRE RCAP2H RCAP2L 230400 0 FF FF 115200 0 FF FE 57600 0 FF FC 38400 0 FF FA 19200 0 FF F4 9600 0 FF E8 4800 0 FF D0 2400 0 FF A0 1200 0 FF 40 600 0 FE 80 300 0 FD 0 150 0 FA 0 110 0 F7 D2 5.3 Watchdog (timer 3) The watchdog timer includes a 18-bit preescaler which is set to 0 when T3 is reloaded. T3 is active only when /EWDG pin is tied to „0‟. T3 must be reloaded by software to avoid T3 rollover and program restart. Reload of T3 is allowed only if WLE watchdog load enable (PCON(4)) is set. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 PCON SMOD -- -- WLE GF1 GF0 PD IDL SMOD: Doubles baud rate bit when timer 1 is used as time generator and serial port is in modes 1,2 or 3 --: Reserved bit WLE: Watchdog load enable. It must be set by software to enable T3 reload. WLE is reset by hardware 13 machine cycles after been set by user software. GF1: General purpose flag bit, user programmable GF0: General purpose flag bit, user programmable PD: Sets power down mode IDL: Sets idle mode Reload of T3 register automatically resets the preescaler and WLE |
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