ATPL00B datasheet(17/152 Pages) ATMEL

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Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

Processor and Architecture

4.1

ADD8051C3A Microcontroller Description

The following document provides a detailed description of the ADD8051C3A architecture and its hardware.

ADD8051C3A is fully compatible with any 8051 legacy microcontroller, however there are some hardware differences

that deserve to be taken into account.

CPU speed has been improved. The machine cycle has been reduced from 12 to 3 clock cycles, and all the instructions

are executed in 1 or 2 machine cycles. Programs are executed a minimum of four times faster than in a standard-8051-

architecture device, achieving x5 speedup for most programs.

A 128KBytes SRAM is embedded on chip. Program memory and External Data (XDATA) memory share this 128Kbytes

SRAM. The lower 64Kbytes are always dedicated to store program memory, while upper 64Kbytes are configurable to

allocate different program and XDATA memory size configurations, depending on bank switching page size (See 4.3).

This document includes a detailed description of registers and peripherals. Some of these items are upgraded versions

of the original 8051 microcontroller circuitry, while others are a simplified version.

Figure 4-1.

ADD8051C3A microcontroller block diagram

Note:

This chapter describes the architecture from the microcontroller point of view. Thus, “on-chip SRAM” is referred

to as “external memory” since “external” instructions like MOVX are necessary to access this memory

device

WATCHDOG

TIMER 2

TIMER 1

TIMER 0

CLOCK

CONTROL

CPU

INTERRUPT

CONTROL

SPI

SERIAL

INTERFACE

USER I/O PORTS

XPROGRAM AND XDATA

ACCESS

256B RAM

(IDATA)

XDATA MAPPED

PERIPHERALS

EXTERNAL

INTERRUPTS

UART 0

UART 1

UART 2

MISO(0,1)

MOSI(0,1) SPICLK(0,1) /SS(0,1)

COUNTER

INPUTS

CLK

DATA

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