PSD833F2 datasheet(59/110 Pages) STMICROELECTRONICS

59 / 110 page

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Port C – Functionality and Structure

Port C can be configured to perform one or more

of the following functions (see Figure 29):

■

MCU I/O Mode

■

CPLD Output – McellBC7-McellBC0 outputs

can be connected to Port B or Port C.

■

CPLD Input – via the Input Macrocells (IMC)

■

Address In – Additional high address inputs

using the Input Macrocells (IMC).

■

In-System Programming (ISP) – JTAG port

can be enabled for programming/erase of the

PSD device. (See the section entitled

PROGRAMMING IN-CIRCUIT USING THE

JTAG SERIAL INTERFACE, page 69 for

more information on JTAG programming.)

■

Open Drain – Port C pins can be configured in

Open Drain Mode

■

Battery Backup features – PC2 can be

configured for a battery input supply, Voltage

Stand-by (VSTBY).

PC4 can be configured as a Battery-on Indicator

(VBATON), indicating when VCC is less than

VBAT.

Port C does not support Address Out mode, and

therefore no Control Register is required.

Pin PC7 may be configured as the DBE input in

certain MCU bus interfaces.

Figure 29. Port C Structure

DATA OUT

REG.

MCELLBC[ 7:0]

ENABLE PRODUCT TERM (.OE)

READ MUX

CPLD - INPUT

DIR REG.

INPUT

MACROCELL

ENABLE OUT

SPECIAL FUNCTION

CONFIGURATION

BIT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT C PIN

DATA OUT

AI02888B

PSD833F2 Datasheet(PDF) 59 Page - STMicroelectronics

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