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PSD833F2 Datasheet(PDF) 84 Page - STMicroelectronics

Part # PSD833F2
Description  Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PDF  110 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD833F2 Datasheet(HTML) 84 Page - STMicroelectronics

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Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)
Symbol
Parameter
Conditions
-70
-90
-15
PT
Aloc
Turbo
Off
Slew
Rate
Unit
Min
Max
Min
Max
Min
Max
fMAXA
Maximum
Frequency
External
Feedback
1/(tSA+tCOA)
38.4
26.32
21.27
MHz
Maximum
Frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10)
62.5
35.71
27.78
MHz
Maximum
Frequency
Pipelined
Data
1/(tCHA+tCLA)
71.4
41.67
35.71
MHz
tSA
Input Setup
Time
7
8
12
+ 2
+ 10
ns
tHA
Input Hold
Time
812
14
ns
tCHA
Clock Input
High Time
9
12
15
+ 10
ns
tCLA
Clock Input
Low Time
9
12
15
+ 10
ns
tCOA
Clock to
Output Delay
21
30
37
+ 10
– 2
ns
tARDA
CPLD Array
Delay
Any macrocell
11
16
22
+ 2
ns
tMINA
Minimum
Clock Period
1/fCNTA
16
28
39
ns



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