PIC18F4539-ESLASHMLSQTP datasheet(212/322 Pages) MICROCHIP

212 / 322 page

PIC18FXX39

DS30485A-page 210

Preliminary

 2002 Microchip Technology Inc.

20.4.2

DATA EEPROM

CODE PROTECTION

The entire Data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of Data EEPROM.

WRTD inhibits external writes to Data EEPROM. The

CPU can continue to read and write Data EEPROM,

regardless of the protection bit settings.

20.4.3

CONFIGURATION REGISTER

PROTECTION

The configuration registers can be write protected. The

WRTC bit controls protection of the configuration regis-

ters. In User mode, the WRTC bit is readable only. WRTC

can only be written via ICSP or an external programmer.

20.5

ID Locations

Eight memory locations (200000h - 200007h) are des-

ignated as ID locations, where the user can store

checksum or other code identification numbers. These

locations are accessible during normal execution

through the TBLRD and TBLWT instructions, or during

program/verify. The ID locations can be read when the

device is code protected.

The sequence for programming the ID locations is sim-

ilar to programming the FLASH memory (see

Section 5.5.1).

20.6

In-Circuit Serial Programming

PIC18FXXX microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware, or a custom

firmware to be programmed.

20.7

In-Circuit Debugger

When the DEBUG bit in configuration register

CONFIG4L is programmed to a '0', the In-Circuit

Debugger functionality is enabled. This function allows

simple debugging functions when used with MPLAB®

IDE. When the microcontroller has this feature

enabled, some of the resources are not available for

general use. Table 20-4 shows which features are

consumed by the background debugger.

TABLE 20-4:

DEBUGGER RESOURCES

To use the In-Circuit Debugger function of the micro-

controller, the design must implement In-Circuit Serial

Programming connections to MCLR/VPP, VDD, GND,

RB7 and RB6. This will interface to the In-Circuit

Debugger module available from Microchip, or one of

the third party development tool companies.

20.8

Low Voltage ICSP Programming

The LVP bit configuration register CONFIG4L enables

low voltage ICSP programming. This mode allows the

microcontroller to be programmed via ICSP using a

VDD source in the operating voltage range. This only

means that VPP does not have to be brought to VIHH,

but can instead be left at the normal operating voltage.

In this mode, the RB5/PGM pin is dedicated to the pro-

gramming function and ceases to be a general purpose

I/O pin. During programming, VDD is applied to the

MCLR/VPP pin. To enter Programming mode, VDD must

be applied to the RB5/PGM, provided the LVP bit is set.

The LVP bit defaults to a ‘1’ from the factory.

If Low Voltage Programming mode is not used, the LVP

bit can be programmed to a '0' and RB5/PGM becomes

a digital I/O pin. However, the LVP bit may only be pro-

grammed when programming is entered with VIHH on

MCLR/VPP.

It should be noted that once the LVP bit is programmed

to ‘0’, only the High Voltage Programming mode is

available and only High Voltage Programming mode

can be used to program the device.

When using low voltage ICSP, the part must be sup-

plied 4.5V to 5.5V, if a bulk erase will be executed. This

includes reprogramming of the code protect bits from

an on-state to an off-state. For all other cases of low

voltage ICSP, the part may be programmed at the nor-

mal operating voltage. This means unique user IDs, or

user code can be reprogrammed or added.

I/O pins

RB6, RB7

Stack

2 levels

Program Memory

512 bytes

Data Memory

10 bytes

Note 1: The High Voltage Programming mode is

always available, regardless of the state

of the LVP bit, by applying VIHH to the

MCLR pin.

2: While in low voltage ICSP mode, the RB5

pin can no longer be used as a general

purpose I/O pin, and should be held low

during normal operation to protect

against inadvertent ICSP mode entry.

3: When using low voltage ICSP program-

ming (LVP), the pull-up on RB5 becomes

disabled. If TRISB bit 5 is cleared,

thereby setting RB5 as an output, LATB

bit 5 must also be cleared for proper

operation.

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