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PIC18F4539-E/MLSQTP Datasheet(PDF) 47 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP Datasheet(HTML) 47 Page - Microchip Technology |
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47 / 322 page  2002 Microchip Technology Inc. Preliminary DS30485A-page 45 PIC18FXX39 IPR2 — — — EEIP BCLIP LVDIP TMR3IP — ---1 1111 29, 79 PIR2 — — — EEIF BCLIF LVDIF TMR3IF — ---0 0000 29, 75 PIE2 — — — EEIE BCLIE LVDIE TMR3IE — ---0 0000 29, 77 IPR1 PSPIP(3) ADIP RCIP TXIP SSPIP — TMR2IP TMR1IP 1111 1111 29, 78 PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF — TMR2IF TMR1IF 0000 0000 29, 74 PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE — TMR2IE TMR1IE 0000 0000 29, 76 TRISE(3) IBF OBF IBOV PSPMODE — Data Direction bits for PORTE 0000 -111 29, 94 TRISD(3) Data Direction Control Register for PORTD 1111 1111 29, 92 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 * * TRISC0 1111 1111 29, 89 TRISB Data Direction Control Register for PORTB 1111 1111 29, 86 TRISA —TRISA6(1) Data Direction Control Register for PORTA -111 1111 29, 83 LATE(3) — — — — — Read PORTE Data Latch, Write PORTE Data Latch ---- -xxx 29, 95 LATD(3) Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 29, 91 LATC LATC7 LATC6 LATC5 LATC4 LATC3 * * LATC0 xxxx xxxx 29, 89 LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 29, 86 LATA —LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 29, 83 PORTE(3) Read PORTE pins, Write PORTE Data Latch ---- -000 29, 95 PORTD(3) Read PORTD pins, Write PORTD Data Latch xxxx xxxx 29, 91 PORTC RC7 RC6 RC5 RC4 RC3 * * RC0 xxxx xxxx 29, 89 PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 29, 86 PORTA —RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 29, 83 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition * These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details. Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear. |
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