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PIC18F4539-E/MLSQTP Datasheet(PDF) 316 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP Datasheet(HTML) 316 Page - Microchip Technology |
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316 / 322 page  PIC18FXX39 DS30485A-page 314 Preliminary 2002 Microchip Technology Inc. Programming, Device Instructions ................................... 211 PSP.See Parallel Slave Port. Pulse Width Modulation (PWM) ....................................... 123 Pulse Width Modulation. See PWM. PUSH ............................................................................... 240 PWM Associated Registers ............................................... 124 CCPR1H:CCPR1L Registers ................................... 123 Duty Cycle ................................................................ 124 Period ....................................................................... 123 TMR2 to PR2 Match ................................................. 123 Q Q Clock ............................................................................ 124 R RAM. See Data Memory RCALL .............................................................................. 241 RCSTA Register SPEN Bit .................................................................. 165 Register File ....................................................................... 39 Registers ADCON0 (A/D Control 0) ......................................... 181 ADCON1 (A/D Control 1) ......................................... 182 CCP1CON and CCP2CON (PWM Control) ............. 123 CONFIG1H (Configuration 1 High) .......................... 196 CONFIG2H (Configuration 2 High) .......................... 197 CONFIG2L (Configuration 2 Low) ............................ 197 CONFIG4L (Configuration 4 Low) ............................ 198 CONFIG5H (Configuration 5 High) .......................... 199 CONFIG5L (Configuration 5 Low) ............................ 199 CONFIG6H (Configuration 6 High) .......................... 200 CONFIG6L (Configuration 6 Low) ............................ 200 CONFIG7H (Configuration 7 High) .......................... 201 CONFIG7L (Configuration 7 Low) ............................ 201 DEVID1 (Device ID 1) .............................................. 202 DEVID2 (Device ID 2) .............................................. 202 EECON1 (Data EEPROM Control 1) ................... 53, 62 File Summary ....................................................... 43–45 INTCON (Interrupt Control) ........................................ 71 INTCON2 (Interrupt Control 2) ................................... 72 INTCON3 (Interrupt Control 3) ................................... 73 IPR1 (Peripheral Interrupt Priority 1) .......................... 78 IPR2 (Peripheral Interrupt Priority 2) .......................... 79 LVDCON (LVD Control) ........................................... 191 PIE1 (Peripheral Interrupt Enable 1) .......................... 76 PIE2 (Peripheral Interrupt Enable 2) .......................... 77 PIR1 (Peripheral Interrupt Request 1) ........................ 74 PIR2 (Peripheral Interrupt Request 2) ........................ 75 RCON (Register Control) ........................................... 80 RCON (RESET Control) ............................................. 50 RCSTA (Receive Status and Control) ...................... 167 SSPCON1 (MSSP Control 1) SPI Mode ......................................................... 127 SSPCON1 (MSSP Control 1), I2C Mode .................. 136 SSPCON2 (MSSP Control 2), I2C Mode .................. 137 SSPSTAT (MSSP Status) SPI Mode ......................................................... 126 SSPSTAT (MSSP Status), I2C Mode ....................... 135 STATUS ..................................................................... 49 STKPTR (Stack Pointer) ............................................ 35 T0CON (Timer0 Control) ............................................ 99 T1CON (Timer 1 Control) ......................................... 103 T2CON (Timer2 Control) .......................................... 107 T3CON (Timer3 Control) .......................................... 109 TRISE ......................................................................... 94 TXSTA (Transmit Status and Control) ..................... 166 WDTCON (Watchdog Timer Control) ...................... 203 RESET ................................................................23, 195, 241 Brown-out Reset (BOR) ........................................... 195 MCLR Reset (During SLEEP) .................................... 23 MCLR Reset (Normal Operation) .............................. 23 Oscillator Start-up Timer (OST) ............................... 195 Power-on Reset (POR) .......................................23, 195 Power-up Timer (PWRT) ......................................... 195 Programmable Brown-out Reset (BOR) .................... 23 RESET Instruction ..................................................... 23 Stack Full Reset ......................................................... 23 Stack Underflow Reset .............................................. 23 Watchdog Timer (WDT) Reset .................................. 23 RETFIE ............................................................................ 242 RETLW ............................................................................ 242 RETURN .......................................................................... 243 Return Address Stack ........................................................ 34 Associated Registers ................................................. 35 Pointer (STKPTR) ...................................................... 34 Top-of-Stack Access .................................................. 34 Revision History ............................................................... 305 RLCF ............................................................................... 243 RLNCF ............................................................................. 244 RRCF ............................................................................... 244 RRNCF ............................................................................ 245 S SCI. See USART SCK ................................................................................. 125 SDI ................................................................................... 125 SDO ................................................................................. 125 Serial Clock, SCK ............................................................ 125 Serial Communication Interface. See USART Serial Data In, SDI ........................................................... 125 Serial Data Out, SDO ....................................................... 125 Serial Peripheral Interface. See SPI Mode SETF ................................................................................ 245 Single Phase Induction Motor Control Module. See Motor Control. ................................................... 113 Slave Select Synchronization .......................................... 131 Slave Select, SS .............................................................. 125 SLEEP ..............................................................195, 205, 246 Software Simulator (MPLAB SIM) .................................... 254 Special Features of the CPU ........................................... 195 Configuration Registers ....................................196–201 Special Function Registers ................................................ 39 Map ............................................................................ 42 SPI Mode Associated Registers ............................................... 133 Bus Mode Compatibility ........................................... 133 Effects of a RESET .................................................. 133 Master Mode ............................................................ 130 Master/Slave Connection ......................................... 129 Overview .................................................................. 125 Serial Clock .............................................................. 125 Serial Data In ........................................................... 125 Serial Data Out ........................................................ 125 Slave Mode .............................................................. 131 Slave Select ............................................................. 125 Slave Select Synchronization .................................. 131 Slave Synch Timing ................................................. 131 SLEEP Operation .................................................... 133 SPI Clock ................................................................. 130 SS .................................................................................... 125 SSPOV Status Flag ......................................................... 155 |
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