PIC18F4539-ESLASHMLSQTP datasheet(107/322 Pages) MICROCHIP

107 / 322 page

 2002 Microchip Technology Inc.

Preliminary

DS30485A-page 105

PIC18FXX39

11.2

Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR1 interrupt, if enabled, is generated on overflow,

which is latched in interrupt flag bit TMR1IF (PIR1<0>).

This

interrupt

can

enabled/disabled

setting/clearing TMR1 interrupt enable bit, TMR1IE

(PIE1<0>).

11.3

Timer1 16-bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 11-2). When the RD16 control bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 high byte buffer. This provides

the user with the ability to accurately read all 16-bits of

Timer1 without having to determine whether a read of

the high byte, followed by a read of the low byte is valid,

due to a rollover between reads.

A write to the high byte of Timer1 must also take place

through the TMR1H buffer register. Timer1 high byte is

updated with the contents of TMR1H when a write

occurs to TMR1L. This allows a user to write all 16 bits

to both the high and low bytes of Timer1 at once.

The high byte of Timer1 is not directly readable or writ-

able in this mode. All reads and writes must take place

through the Timer1 high byte buffer register. Writes to

TMR1H do not clear the Timer1 prescaler. The

prescaler is only cleared on writes to TMR1L.

TABLE 11-1:

REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

All Other

RESETS

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x 0000 000u

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

—

TMR2IF

TMR1IF 0000 0000 0000 0000

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

—

TMR2IE

TMR1IE 0000 0000 0000 0000

IPR1

PSPIP(1)

ADIP

RCIP

TXIP

SSPIP

—

TMR2IP

TMR1IP 0000 0000 0000 0000

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

T1CON

RD16

—

T1CKPS1 T1CKPS0

—

T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Legend:

= unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.

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