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PIC18F4539-E/MLSQTP Datasheet(PDF) 113 Page - Microchip Technology |
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PIC18F4539-E/MLSQTP Datasheet(HTML) 113 Page - Microchip Technology |
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113 / 322 page ![]() 2002 Microchip Technology Inc. Preliminary DS30485A-page 111 PIC18FXX39 13.2 Timer3 Interrupt The TMR3 Register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled/disabled by setting/clearing TMR3 interrupt enable bit, TMR3IE (PIE2<1>). TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on All Other RESETS INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR2 — — — EEIF BCLIF LVDIF TMR3IF — ---0 0000 ---0 0000 PIE2 — — — EEIE BCLIE LVDIE TMR3IE — ---0 0000 ---0 0000 IPR2 — — — EEIP BCLIP LVDIP TMR3IP — ---1 1111 ---1 1111 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu T1CON RD16 — T1CKPS1 T1CKPS0 — T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu T3CON RD16 — T3CKPS1 T3CKPS0 — T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. |
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