CY28317-2

....................... Document #: 38-07094 Rev. *B Page 8 of 20

Bit 5

WD_TIMER4

1

These bits store the time-out value of the Watchdog Timer. The scale of the

timer is determined by the prescaler.

The timer can support a value of 150 ms to 4.8 sec when the prescaler is set

to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec

to 80 sec.

When the Watchdog Timer reaches “0,” it will set the WD_TO_STATUS bit and

generate Reset if RST_EN_WD is enabled.

Bit 4

WD_TIMER3

1

Bit 3

WD_TIMER2

1

Bit 2

WD_TIMER1

1

Bit 1

WD_TIMER0

1

Bit 0

WD_PRE_SC

ALER

0

0 = 150 ms

1 = 2.5 sec

Byte 6: Watchdog Timer Register (continued)

Bit

Name

Default

Pin Description

Byte 7: Control Register 7

Bit

Pin#

Name

Default

Pin Description

Bit 7

–

Reserved

0

Reserved

Bit 6

25

24_48MHz_DRV

1

0 = Norm, 1 = High Drive

Bit 5

26

48MHz_DRV

1

0 = Norm, 1 = High Drive

Bit 4

–

Reserved

0

Reserved

Bit 3

–

Reserved

0

Reserved

Bit 2

–

Reserved

0

Reserved

Bit 1

–

Reserved

0

Reserved

Bit 0

–

Reserved

0

Reserved

Byte 8: Vendor ID and Revision ID Register (Read Only)

Bit

Name

Default

Pin Description

Bit 7

Revision_ID3

0

Revision ID bit[3]

Bit 6

Revision_ID2

0

Revision ID bit[2]

Bit 5

Revision_ID1

0

Revision ID bit[1]

Bit 4

Revision_ID0

0

Revision ID bit[0]

Bit 3

Vendor_ID3

1

Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read-only.

Bit 2

Vendor_ID2

0

Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read-only.

Bit 1

Vendor _ID1

0

Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read-only.

Bit 0

Vendor _ID0

0

Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read-only.

Byte 9: System RESET and Watchdog Timer Register

Bit

Name

Default

Pin Description

Bit 7

SDRAM_DRV

0

SDRAM clock output drive strength

0 = Normal

1 = High Drive

Bit 6

PCI_DRV

0

PCI clock output drive strength

0 = Normal

1 = High Drive

Bit 5

Reserved

0

Reserved

Bit 4

RST_EN_WD

0

This bit will enable the generation of a Reset pulse when a Watchdog Timer

time-out occurs.

0 = Disabled

1 = Enabled