DG534A/538A

Vishay Siliconix

www.vishay.com

16

Document Number: 70069

S-05734—Rev. G, 29-Jan-02

APPLICATIONS (CONT'D)

These devices feature an address readback (Tally) facility,

whereby the last address written to the device may be output

to the system. This allows improved status monitoring and

hand shaking without additional external components.

This function is controlled by the I/O pin, which directly

addresses the tri-state buffers connected to the EN and

address pins. EN and address pins can be assigned to accept

data (when I/O = 0; WR = 0; RS = 1), or output data (when I/O =

1; WR = 1; RS = 1), or to reflect a high impedance and latched

state (when I/O = 0; WR = 1; RS = 1).

When I/O is high, the address output can sink or source

shifting.

Further control pins facilitate easy microprocessor interface.

On chip address, data latches are activated by WR, which

serves as a strobe type function eliminating the need for

peripheral latch or memory I/O port devices. Also, for ease of

interface, a direct reset function (RS) allows all latches to be

cleared and switches opened. Reset should be used during

power up, etc., to avoid spurious switch action. See Figure 16.

Channel address data can only be entered during WR low,

when the address latches are transparent and I/O is low.

Similarly, address readback is only operational when WR and

I/O are high.

The Siliconix CLC410 Video amplifier is recommended as an

output buffer to reduce insertion loss and to drive coaxial

cables. For low power video routing applications or for unity

gain input buffers CLC111/CLC114 are recommended.

8

7

6

5

4

3

2

1

0

0

2468

10

12

14

16

18

(V)

FIGURE 15.

Reset

Address

Decoder

WR

Video

Bus

Data

Bus

Address Bus

Data Bus

I/O

75

W

75

W

75

W

75

W

CLC410

CLC410

CLC410

CLC410

DG534A

DG534A

FIGURE 16.

DG534A in a Video Matrix

WR

EN

RS

EN

WR

RS