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AT89C51RC2-3CSIM Datasheet(PDF) 13 Page - ATMEL Corporation |
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AT89C51RC2-3CSIM Datasheet(HTML) 13 Page - ATMEL Corporation |
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13 / 125 page ![]() 13 AT89C51RB2/RC2 4180B–8051–04/03 Functional Block Diagram Figure 3. Functional Oscillator Block Diagram Prescaler Divider • A hardware RESET puts the prescaler divider in the following state: • CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature) • Any value between FFh down to 00h can be written by software into CKRL register in order to divide frequency of the selected oscillator: • CKRL = 00h: minimum frequency F CLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode) F CLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode) • CKRL = FFh: maximum frequency F CLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode) F CLK CPU = FCLK PERIPH = FOSC (X2 Mode) F CLK CPU and FCLK PERIPH In X2 Mode, for CKRL<>0xFF: In X1 Mode, for CKRL<>0xFF then: Xtal2 Xtal1 Osc CLK Idle CPU clock CKRL Reload 8-bit Prescaler-Divider Reset Peripheral Clock :2 X2 0 1 F OSC CKCON0 CLK PERIPH CPU CKRL = 0xFF? 0 1 F CPU F = CLKPERIPH F OSC 2 255 CKRL – () × ----------------------------------------------- = F CPU F = CLKPERIPH F OSC 4 255 CKRL – () × ----------------------------------------------- = |
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