EN29F800 datasheet(13/38 Pages) ETC

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EN29F800

Rev. E, Issue Date: 2001/07/05

WRITE OPERATION STATUS

DQ7

DATA

Polling

The EN29F800 provides DATA Polling on DQ7 to indicate to the host system the status of the

embedded operations. The DATA Polling feature is active during the Byte Programming, Sector

Erase, Chip Erase, Erase Suspend. (See Table 6)

When the Byte Programming is in progress, an attempt to read the device will produce the

complement of the data last written to DQ7. Upon the completion of the Byte Programming, an

attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,

DATA polling is valid after the rising edge of the fourth WE or CE pulse in the four-cycle sequence.

When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the

DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7

output during the read. For Chip Erase, the DATA polling is valid after the rising edge of the sixth

WE or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last

rising edge of the sector erase WE or CE pulse.

DATA Polling must be performed at any address within a sector that is being programmed or erased

and not a protected sector. Otherwise, DATA polling may give an inaccurate result if the address

used is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the

output enable ( OE ) is low. This means that the device is driving status information on DQ7 at one

instant of time and valid data at the next instant of time. Depending on when the system samples the

DQ7 output, it may read the status of valid data. Even if the device has completed the embedded

operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid

data on DQ0-DQ7 will be read on the subsequent read attempts.

The flowchart for DATA Polling (DQ7) is shown on Flowchart 5. The DATA Polling (DQ7) timing

diagram is shown in Figure 8.

RY/BY: Ready/Busy

The RY/BY is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the

command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together

in parallel with a pull-up resistor to Vcc.

In the output is low, signifying Busy, the device is actively erasing or programming. This includes

programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is

ready to read array data (including during the Erase Suspend mode), or is in the standby mode.

DQ6 Toggle Bit I

The EN29F800 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the

embedded programming and erase operations. (See Table 6)

During an embedded Program or Erase operation, successive attempts to read data from the device

at any address (by toggling OE or CE ) will result in DQ6 toggling between “zero” and “one”. Once

the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be

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