ISL8225MEVAL4Z datasheet(23/34 Pages) RENESAS

23 / 34 page

ISL8225M

FN7822 Rev 2.00

Page 23 of 34

December 8, 2014

Selection of Output Capacitors

The ISL8225M is designed for low output voltage ripple. The

output voltage ripple and transient requirements can be met with

bulk output capacitors (COUT) that have adequately low ESR.

COUT can be a low ESR tantalum capacitor, a low ESR polymer

capacitor, or a ceramic capacitor. The typical capacitance is

330µF, and decoupled ceramic output capacitors are used for

each phase. See Tables 1 and 2 for more capacitor information.

Internally optimized loop compensation provides sufficient

stability margins for all ceramic capacitor applications, with a

recommended total value of 300µF per phase. Additional output

filtering may be needed if further reduction of output ripple or

dynamic transient spike is required.

EN/FF Turn ON/OFF

Each output of the ISL8225M can be turned on/off independently

through the EN/FF pins. For parallel use, tie all EN/FF pins together.

Since this pin has the feed-forward function, the voltage on this pin

can actively adjust the loop gain to be constant for variable input

voltage. Please refer to Table 1 to select the resistor divider for

commonly used conditions. Otherwise, use the following procedures

to finish the EN/FF design:

1. A resistor divider from VIN to GND is recommended to set the

EN/FF voltage between 1.25V to 5.0V. The resistor divider

ratio is recommended to be between 3/1 to 4/1 (as shown in

Figure 21) with a resistor divider at 7.15kΩ/2.05kΩ.

2. Check EN turn-on hysteresis (Recommend VEN_HYS >0.3V):

where:

•RUP is the top resistor of the resistor divider

• N is the total number of the EN/FF pins tied to the resistor divider

3. Set the maximum current flowing through the top pull-up

resistor RUP to below 7mA (considering EN/FF is pulled to

ground (VEN/FF = 0)). Refer to Figure 25; a 3.01kΩ/1kΩ

resistor is used to allow for the input voltage from 5V to 20V

operation. In addition, the maximum current flowing through

R5 is 6.6mA (<7mA).

4. If the EN/FF is controlled by system EN signal instead of the

input voltage, we recommend setting the fixed EN/FF voltage

to about 1/3.5 of the input voltage. If the input voltage is 12V,

a 3.3V system EN signal can be tied to EN/FF pin directly.

5. If the input voltage is below 5.5V, it is recommended to have

EN/FF voltage >1.5V to have better stability. The input voltage

can be directly tied to the VCC pin to disable the internal LDO.

6. A 1nF capacitor is recommended on the EN/FF pin to avoid

the noise injecting into the feed-forward loop.

Thermal Considerations

The ISL8225M QFN package offers typical junction to ambient

thermal resistance

JA of approximately 10°C/W at natural

convection (~5.8°C/W at 400LFM) with a typical 4-layer PCB.

Therefore, use Equation 5 to estimate the module junction

temperature:

where:

•Tjunction is the module internal maximum temperature (°C)

•Tambient is the system ambient temperature (°C)

• P is the total power loss of the module package (W)

•

JA is the thermal resistance of module junction to ambient

If the calculated temperature, Tjunction, is over the required

design target, the extra cooling scheme is required. Please refer

to “Current Derating” on page 28 for adding air flow.

Functional Description

Initialization

Initially, the Power-On Reset (POR) circuits continuously monitor

bias voltages (VCC) and voltage at the EN/FF pin. The POR

function initiates soft-start operation 384 clock cycles

after: (1) the EN pin voltage is pulled above 0.8V, (2) all input

supplies exceed their POR thresholds, and (3) the PLL locking

time expires. The Enable pin can be used as a voltage monitor

and to set the desired hysteresis, with an internal 30µA sinking

current going through an external resistor divider. The sinking

current is disengaged after the system is enabled. This feature is

specially designed for applications that require higher input rail

POR for better undervoltage protection. For example, in 12V

applications, RUP = 53.6kΩ and RDOWN = 5.23kΩ sets the

turn-on threshold (VEN_RTH) to 10.6V and the turn-off threshold

(VEN_FTH) to 9V, with 1.6V hysteresis (VEN_HYS).

During shutdown or fault conditions, soft-start is quickly reset,

and the gate driver immediately changes state (<100ns) when

input drops below POR.

Enable and Voltage Feed-forward

Voltage applied to the EN/FF pin is fed to adjust the sawtooth

amplitude of the channel. Sawtooth amplitude is set to 1.25 times

the corresponding FF voltage when the module is enabled. This

configuration helps maintain a constant gain. This configuration

also helps maintain input voltage to achieve optimum loop response

over a wide input voltage range.

A 384-cycle delay is added after the system reaches its rising

POR and prior to soft-start. The RC timing at the FF pin should be

small enough to ensure that the input bus reaches its static state

and that the internal ramp circuitry stabilizes before soft-start. A

large RC could cause the internal ramp amplitude not to

synchronize with the input bus voltage during output start-up or

when recovering from faults. A 1nF capacitor is recommended as

a starting value for typical applications.

In a multi-module system, with the EN pins are wired together, all

modules can immediately turn off, at one time, when a fault

condition occurs in one or more modules. A fault pulls the EN pin

low, disabling all modules, and does not create current bounce;

thus, no single channel is overstressed when a fault occurs.

Because the EN pins are pulled down under fault conditions, the

pull-up resistor (RUP) should be scaled to sink no more than 7mA

current from the EN pin. Essentially, the EN pins cannot be

directly connected to VCC.

VEN HYS

–



UP 3x10

–



(EQ. 4)

Tjunction





Tambient

(EQ. 5)

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