ISL8225MEVAL4Z datasheet(28/34 Pages) RENESAS

28 / 34 page

ISL8225M

FN7822 Rev 2.00

Page 28 of 34

December 8, 2014

Current Derating

Experimental power loss curves (Figures 35 and 36), along with

JA from thermal modeling analysis, can be used to evaluate the

thermal consideration for the module. Derating curves are

derived from the maximum power allowed while maintaining

temperature below the maximum junction temperature of

+120°C (Figures 37 through 42). The maximum +120°C

junction temperature is considered for the module to load the

current consistently and it provides the 5°C margin of safety

from the rated junction temperature of +125°C. If necessary,

customers can adjust the margin of safety according to the real

applications. All derating curves are obtained from the tests on

the ISL8225MEVAL4Z evaluation board. In the actual

application, other heat sources and design margins should be

considered.

Package Description

The ISL8225M is integrated into a quad flatpack no lead

package (QFN). This package has such advantages as good

thermal and electrical conductivity, low weight, and small size.

The QFN package is applicable for surface mounting technology

and is becoming more common in the industry. The ISL8225M

contains several types of devices, including resistors, capacitors,

inductors, and control ICs. The ISL8225M is a copper lead-frame

based package with exposed copper thermal pads, which have

good electrical and thermal conductivity. The copper lead frame

and multi-component assembly are over-molded with polymer

mold compound to protect these devices.

The package outline, typical PCB layout pattern, and typical

stencil pattern design are shown in the L26.17x17 package

outline drawing on page 28. Figure 48 shows typical reflow

profile parameters. These guidelines are general design rules.

Users can modify parameters according to specific applications.

PCB Layout Pattern Design

The bottom of ISL8225M is a lead-frame footprint, which is

attached to the PCB by surface mounting. The PCB layout pattern

is shown in the L26.17x17 package outline drawing on page 33.

The PCB layout pattern is essentially 1:1 with the QFN exposed

pad and the I/O termination dimensions, except that the PCB

lands are slightly longer than the QFN terminations by about

0.2mm (0.4mm max). This extension allows for solder filleting

around the package periphery and ensures a more complete and

inspectable solder joint. The thermal lands on the PCB layout

should match 1:1 with the package exposed die pads.

Thermal Vias

A grid of 1.0mm to 1.2mm pitched thermal vias, which drops

down and connects to buried copper planes, should be placed

under the thermal land. The vias should be about 0.3mm to

0.33mm in diameter, with the barrel plated to about 2.0 ounce

copper. Although adding more vias (by decreasing pitch)

improves thermal performance, it also diminishes results as

more vias are added. Use only as many vias as are needed for

the thermal land size and as your board design rules allow.

Stencil Pattern Design

Reflowed solder joints on the perimeter I/O lands should have

about a 50µm to 75µm (2mil to 3mil) standoff height. The solder

paste stencil design is the first step in developing optimized,

reliable solder joins. The stencil aperture size to land size ratio

should typically be 1:1. Aperture width may be reduced slightly to

help prevent solder bridging between adjacent I/O lands.

To reduce solder paste volume on the larger thermal lands, an

array of smaller apertures instead of one large aperture is

recommended. The stencil printing area should cover 50% to

80% of the PCB layout pattern. A typical solder stencil pattern is

shown in the L26.17x17 package outline drawing on page 33.

The gap width between pads is 0.6mm. Consider the symmetry

of the whole stencil pattern when designing the pads.

A laser-cut, stainless-steel stencil with electropolished

trapezoidal walls is recommended. Electropolishing smooths the

aperture walls, resulting in reduced surface friction and better

paste release, which reduces voids. Using a trapezoidal section

aperture (TSA) also promotes paste release and forms a

brick-like paste deposit, which assists in firm component

placement. A 0.1mm to 0.15mm stencil thickness is

recommended for this large-pitch (1.0mm) QFN.

KELVIN CONNECTIONS

FOR THE VSENS LINES

CIN2

CIN1

COUT1

COUT2

PGND

VOUT1

VOUT2

PHASE1

PHASE2

PGND

VIN2

VIN1

SGND

PGND

KELVIN CONNECTIONS

FOR THE VSENS LINES

PIN 1

TO LOAD

FIGURE 34. RECOMMENDED LAYOUT

OPTIONAL SNUBBER

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