ISL8225MEVAL4Z datasheet(27/34 Pages) RENESAS

27 / 34 page

ISL8225M

FN7822 Rev 2.00

Page 27 of 34

December 8, 2014

Two Phase Parallel Mode Operation

When ISL8225M operates in 2-phase mode, the current sensing

and sharing circuit keeps each channel's current in balance.

After a typical 175nS blanking period, with respect to the falling

edge of the PWM pulse of each channel, the voltage developed

across rDS(ON) of the low side MOSFETs is filtered and sampled

as the sensed current. If the other phase's high-side MOSFET is

turned on right at the moment when current is sensed, the

switching noise can distort the sensed current signal, which may

result in low frequency output ripple. For high output voltage of

>5V, the low frequency ripple is worse due to higher switching

noise at higher input voltage. Because of the 175ns current

sensing blanking time, if the second channel has 180° phase lag

with respect to the first channel, the low frequency ripple

typically appears when the module operates at around 40% duty

cycle depending upon switching frequency. To solve this problem,

240° phase shift (Mode 6 of Table 3) can be used instead of the

180° phase shift (Mode 5A of Table 3). Figure 23 shows a typical

application with 240° phase shift.

All other conditions equal, the module with 180° phase shift has

lower input ripple and output ripple than the module with 240°

phase shift, thus the selection of the optimum operation mode

should be based on the input voltage. Table 7 shows the

operation mode selection to avoid low frequency for 6.5V and

7.5V output applications with 750kHz switching frequency.

Please refer to Table 3 on page 21 for more information about

each operation mode.

Layout Guide

To achieve stable operation, low losses, and good thermal

performance, some layout considerations are necessary

(Figure 34).

• VOUT1, VOUT2, PHASE1, PHASE2, PGND, VIN1 and VIN2

should have large, solid planes. Place enough thermal vias to

connect the power planes in different layers under or around

the module.

• Place high-frequency ceramic capacitors between VIN, VOUT,

and PGND, as closely to the module as possible in order to

minimize high-frequency noise.

• Use remote sensed traces to the regulation point to achieve

tight output voltage regulation, and keep the sensing traces

close to each other in parallel.

• PHASE1 and PHASE2 pads are switching nodes that generate

switching noise. Keep these pads under the module. For

noise-sensitive applications, it is recommended to keep phase

pads only on the top and inner layers of the PCB. Also, do not

place phase pads exposed to the outside on the bottom layer

of the PCB.

• Avoid routing any noise-sensitive signal traces, such as the

VSEN+, VSEN-, ISHARE, COMP and VMON sensing points, near

the PHASE pins.

• Use a separated SGND ground copper area for components

connected to signal ground pins. Connect SGND to PGND with

multiple vias underneath the unit in one location to avoid the

noise coupling, as shown in Figure 34 Don't ground vias

surrounded by the noisy planes of VIN, PHASE and VOUT. For

dual output applications, the SGND to PGND vias are preferred

to be as close as possible to SGND pin.

• Optional snubbers can be put on the bottom side of the board

layout, connecting the PHASE to PGND planes, as shown in

Figure 34.

TABLE 7. OPERATION MODE SETTING FOR 6.5V AND 7.5V OUTPUT APPLICATION

VIN

(V)

OPERATION

MODE

PHASE SHIFT

BETWEEN

PHASES

VSEN2-

VSEN2+

CLKOUT

VMON2

MODE

11 to 13.9

6.5

180°

VCC

N/C

VMON1 OR

DIVIDER

SGND

13.9 to

15.6

6.5

240°

VCC

SGND

N/C

953Ω//22nF

VCC

15.6 to 20

6.5

180°

VCC

N/C

VMON1 OR

DIVIDER

SGND

11 to 15

7.5

180°

VCC

N/C

VMON1 OR

DIVIDER

SGND

15 to 20

7.5

240°

VCC

SGND

N/C

953Ω//22nF

VCC

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