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AT89C51ED2-RDTIM Datasheet(PDF) 80 Page - ATMEL Corporation |
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AT89C51ED2-RDTIM Datasheet(HTML) 80 Page - ATMEL Corporation |
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80 / 137 page  80 AT89C51RD2/ED2 4235E–8051–04/04 Table 57. IPL1 Register IPL1 - Interrupt Priority Register (B2h) Reset Value = XXXX X000b Bit addressable 76 54 32 1 0 - - - - - SPIL TWIL KBDL Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2 SPIL SPI interrupt Priority bit Refer to SPIH for priority level. 1- Reserved The value read from this bit is indeterminate. Do not set this bit. 0 KBDL Keyboard interrupt Priority bit Refer to KBDH for priority level. |
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