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AT89C51ED2-RDTIM Datasheet(PDF) 39 Page - ATMEL Corporation |
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AT89C51ED2-RDTIM Datasheet(HTML) 39 Page - ATMEL Corporation |
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39 / 137 page  39 AT89C51RD2/ED2 4235E–8051–04/04 Table 23. CCON Register CCON - PCA Counter Control Register (D8h) Reset Value = 00X0 0000b Not bit addressable The watchdog timer function is implemented in Module 4 (See Figure 19). The PCA interrupt system is shown in Figure 17. 76 54 32 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic Description 7CF PCA Counter Overflow flag Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. 6CR PCA Counter Run control bit Must be cleared by software to turn the PCA counter off. Set by software to turn the PCA counter on. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4 CCF4 PCA Module 4 interrupt flag Must be cleared by software. Set by hardware when a match or capture occurs. 3 CCF3 PCA Module 3 interrupt flag Must be cleared by software. Set by hardware when a match or capture occurs. 2 CCF2 PCA Module 2 interrupt flag Must be cleared by software. Set by hardware when a match or capture occurs. 1 CCF1 PCA Module 1 interrupt flag Must be cleared by software. Set by hardware when a match or capture occurs. 0 CCF0 PCA Module 0 interrupt flag Must be cleared by software. Set by hardware when a match or capture occurs. |
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