P89LPC913 datasheet(30/63 Pages) PHILIPS

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Philips Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 03 — 17 December 2004

30 of 63

9397 750 14468

• SFR

Special Function Registers. Selected CPU registers and peripheral control and

status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC912/913/914 has 1 kB of on-chip Code memory.

9.10 Interrupts

The P89LPC912/913/914 uses a four priority level interrupt structure. This allows

great ﬂexibility in controlling the handling of the many interrupt sources.

The P89LPC912 supports 7 interrupt sources: timers 0 and 1, brownout detect,

Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI.

The P89LPC913 and P89LPC914 devices support 10 interrupt sources: timers 0 and

1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect,

Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI.

Each interrupt source can be individually enabled or disabled by setting or clearing a

bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a

global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt,

but not by another interrupt of the same or lower priority. The highest priority interrupt

service cannot be interrupted by any other interrupt source. If two requests of

different priority levels are pending at the start of an instruction, the request of higher

priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an

internal polling sequence determines which request is serviced. This is called the

arbitration ranking. Note that the arbitration ranking is only used to resolve pending

requests of the same priority level.

9.10.1

External interrupt inputs

The P89LPC912/913/914 has a Keypad Interrupt function. This can be used as an

external interrupt input.

If enabled when the P89LPC912/913/914 is put into Power-down or Idle mode, the

interrupt will cause the processor to wake-up and resume operation. Refer to Section

9.13 “Power reduction modes” for details.

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