M36LLR8760 datasheet(7/18 Pages) STMICROELECTRONICS

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M36L0R7050T0, M36L0R7050B0

It is not allowed to set EF at VIL, E1P at VIL and E2P

at VIH at the same time.

PSRAM Output Enable (GP). The Output En-

able, GP, provides a high speed tri-state control,

allowing fast read/write cycles to be achieved with

the common I/O data bus.

PSRAM Write Enable (WP). The Write Enable,

WP, controls the Bus Write operation of the device.

PSRAM Upper Byte Enable (UBP). The Upper

Byte Enable, UBP, gates the data on the Upper

Byte Data Inputs/Outputs (DQ8-DQ15) to or from

the upper part of the selected address during a

Write or Read operation.

PSRAM Lower Byte Enable (LBP). The Lower

Byte Enable, LBP, gates the data on the Lower

Byte Data Inputs/Outputs (DQ0-DQ7) to or from

the lower part of the selected address during a

Write or Read operation.

VDDF Supply Voltage. VDDF provides the power

supply to the internal cores of the Flash memory

component. It is the main power supply for all

Flash operations (Read, Program and Erase).

VDDP Supply Voltage. The VDDP Supply Volt-

age supplies the power for all PSRAM operations

(Read, Write, etc.) and for driving the refresh logic,

even when the device is not being accessed.

VDDQ Supply Voltage. VDDQ provides the power

supply for the Flash Memory I/O pins. This allows

all Outputs to be powered independently of the

Flash Memory core power supply, VDDF.

VPPF Program Supply Voltage. VPPF is both a

Flash control input and a Flash power supply pin.

The two functions are selected by the voltage

range applied to the pin.

If VPPF is kept in a low voltage range (0V to VDDQ)

VPPF is seen as a control input. In this case a volt-

age lower than VPPLKF gives an absolute protec-

tion against Program or Erase, while VPPF > VPP1F

enables these functions (see Tables 7 and 8, DC

Characteristics for the relevant values). VPPF is

only sampled at the beginning of a Program or

Erase; a change in its value after the operation has

started does not have any effect and Program or

Erase operations continue.

If VPPF is in the range of VPPHF it acts as a power

supply pin. In this condition VPPF must be stable

until the Program/Erase algorithm is completed.

VSS Ground. VSS is the common ground refer-

ence for all voltage measurements in the Flash

(core and I/O Buffers) and PSRAM chips.

Note: Each Flash memory device in a system

should have their supply voltage (VDDF) and

the program supply voltage VPPF decoupled

with a 0.1µF ceramic capacitor close to the pin

(high frequency, inherently low inductance ca-

pacitors should be as close as possible to the

package). See Figure 6., AC Measurement

Load Circuit. The PCB track widths should be

sufficient to carry the required VPPF program

and erase currents.

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