M36LLR8760 datasheet(4/18 Pages) STMICROELECTRONICS

4 / 18 page

M36L0R7050T0, M36L0R7050B0

4/18

SUMMARY DESCRIPTION

The M36L0R7050T0 and M36L0R7050B0 com-

bine two memory devices in a Multi-Chip Package:

a 128-Mbit, Multiple Bank Flash memory, the

M30L0R7000T0 or M30L0R7000B0, and a 32-

Mbit PseudoSRAM, the M69AR048B. Recom-

mended operating conditions do not allow more

than one memory to be active at the same time.

The memory is offered in a Stacked TFBGA88

(8x10mm, 8x10 ball array, 0.8mm pitch) package.

In addition to the standard version, the packages

are also available in Lead-free version, in compli-

ance with JEDEC Std J-STD-020B, the ST ECO-

PACK 7191395 Specification, and the RoHS

(Restriction of Hazardous Substances) directive.

All packages are compliant with Lead-free solder-

ing processes.

The memory is supplied with all the bits erased

(set to ‘1’).

Figure 2. Logic Diagram

Table 1. Signal Names

Note: 1. A22-A21 are not connected to the PSRAM component.

AI08731

A0-A22

DQ0-DQ15

M36L0R7050T0

M36L0R7050B0

RPF

WPF

E1P

UBP

LBP

VSS

VDDF

VPPF

VDDP

WAITF

VDDQ

E2P

A0-A22 (1)

Address Inputs

DQ0-DQ15

Common Data Input/Output

VDDF

Power Supply for Flash Memory

VDDQ

Flash Memory Power Supply for I/O

Buffers

VPPF

Flash Optional Supply Voltage for Fast

Program and Erase

VSS

Ground

VDDP

PSRAM Power Supply

Not Connected Internally

Do Not Use as Internally Connected

Flash Memory

Latch Enable Input

Chip Enable Input

Output Enable Input

Write Enable Input

RPF

Reset Input

WPF

Write Protect Input

Burst Clock

WAITF

Wait Data in Burst Mode

PSRAM

E1P

Chip Enable Input

Output Enable Input

Write Enable Input

E2P

Power-down Input

UBP

Upper Byte Enable Input

LBP

Lower Byte Enable Input

M36LLR8760 Datasheet(PDF) 4 Page - STMicroelectronics

M36LLR8760 Datasheet(HTML) 4 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL