GMS77C1001 datasheet(37/44 Pages) HYNIX

37 / 44 page

GMS77C1000/GMS77C1001

July. 2001 Ver. 1.1

A power-up example where RESET is not tied to VDD is

shown in Figure 14-2. VDD is allowed to rise and stabilize

before bringing RESET high. The chip will actually come

out of reset TIRT after RESET goes high and POR, PFDR

is released.

In Figure 14-3, the on-chip Power-On Reset feature is be-

ing used (RESET and VDD are tied together). The VDD is

stable before the internal reset timer times out and there is

no problem in getting a proper reset. However, Figure 14-

4 depicts a problem situation where VDD rises too slowly.

The time between when the IRT senses a high on the RE-

SET/VPP pin, and when the RESET/VPP pin (and VDD)

actually reach their full value, is too long. In this situation,

when the internal reset timer times out, VDD has not

reached the VDD (min) value and the chip is, therefore, not

guaranteed to function correctly. For such situations, we

recommend that external R circuits be used to achieve

longer POR delay times (Figure 14-5).

Note: When the device starts normal operation (exits the

reset condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be meet to

ensure operation. If these conditions are not met,

the device must be held in reset until the operating

conditions are met.

FIGURE 14-3 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): FAST VDD RISE TIME

FIGURE 14-4 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): SLOW VDD RISE TIME

VDD

RESET

INTERNAL POR

IRT TIMER-OUT

INTERNAL RESET

TIRT

VDD

RESET

INTERNAL POR

IRT TIMER-OUT

INTERNAL RESET

TIRT

- When VDD rise slowly, the TIRT time-out expires long before VDD has reached its final value.

In this example, the chip will reset properly if, V1

≥ VDDmin.

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