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56F8014 Datasheet(PDF) 40 Page - Freescale Semiconductor, Inc |
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56F8014 Datasheet(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 124 page  56F8014 Technical Data, Rev. 3 40 Freescale Semiconductor Preliminary Table 4-20 System Integration Module Registers Address Map (SIM_BASE = $00 F140) Register Acronym Address Offset Register Description SIM_CTRL $0 Control Register SIM_RSTAT $1 Reset Status Register SIM_SWC0 $2 Software Control Register 0 SIM_SWC1 $3 Software Control Register 1 SIM_SWC2 $4 Software Control Register 2 SIM_SWC3 $5 Software Control Register 3 SIM_MSHID $6 Most Significant Half JTAG ID SIM_LSHID $7 Least Significant Half JTAG ID SIM_PWR $8 Power Control Register Reserved SIM_CLKOUT $A Clock Out Select Register SIM_GPS $B GPIO Peripheral Select Register SIM_PCE $C Peripheral Clock Enable Register SIM_IOSAHI $D I/O Short Address Location High Register SIM_IOSALO $E I/O Short Address Location Low Register Table 4-21 Power Supervisor Registers Address Map (PS_BASE = $00 F160) Register Acronym Address Offset Register Description PS_CTRL $0 Control Register PS_STAT $1 Status Register |
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