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DSP56857 Datasheet(PDF) 306 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 306 Page - Freescale Semiconductor, Inc |
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306 / 662 page ![]() Signal Descriptions 5685X Digital Signal Controller User Manual, Rev. 4 12-6 Freescale Semiconductor 12.3.2.1 ESSI Transmit Clock (SCK) This pin can be configured as either an input or an output pin. This clock signal is used by all the enabled transmitters and the receiver in Synchronous modes or by Transmitter 0 in Asynchronous modes. Please see Table 12-3 for details about how to configure this pin. Note: Although an external serial clock can be independent of and asynchronous to the system clock, the external ESSI clock frequency must not exceed FIPBus_CLK/4, and each ESSI clock phase must exceed the minimum of 1.5 IPBus_CLK cycles. 12.3.2.2 ESSI Serial Control Signal 0 (SC0) The function of this signal is determined by the programmer selecting either Synchronous or Asynchronous mode, according to data in Table 12-4. In Asynchronous mode, this signal is used for the receive clock I/O. In Synchronous mode, this signal is used as the transmitter data out Table 12-3. ESSI Clock Sources Controls RX Clock TX Clock SYN SCKD SCD0 Pin Source Pin Direction Asynchronous 0 0 0 SC0 External SCK External 0 0 1 SC0 Internal SCK External 0 1 0 SC0 External SCK Internal 0 1 1 SC0 Internal SCK Internal Synchronous 1 0 x SCK External SCK External 1 1 x SCK Internal SCK Internal Table 12-4. ESSI Frame Sync Sources Controls RX Clock Frame Sync TX Frame Sync SYN SCD2 SCD1 Pin Source Pin Direction Asynchronous 0 0 0 SC1 External SC2 External 0 0 1 SC1 Internal SC2 External 0 1 0 SC1 External SC2 Internal 0 1 1 SC1 Internal SC2 Internal Synchronous 1 0 x SC2 External SC2 External 1 1 x SC2 Internal SC2 Internal |
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