DSP56857 datasheet(358/662 Pages) FREESCALE

358 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

12-58

Freescale Semiconductor

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1 = The transmit sequence proceeds normally. Data is transferred from the STX register

(or TXFIFO, if enabled) to the Shift register during slot N. Appropriate flags are set.

The DSC is interrupted only for enabled slots. Data written to the STX register when the

Transmitter Empty (or Transmit FIFO Empty) Interrupt Request is being serviced is transmitted

in the next enabled transmit time slot.

The TSM slot mask does not conflict with the STSR. Even if a slot is enabled in the TSM

transmitters during the next transmission slot. Setting the bits in the TSM register affects the next

frame transmission. The frame currently being transmitted is not affected by the new TSM

setting. If the TSM is read, it shows the current setting.

An ESSI reset (ESSIEN = 0) does not affect the contents of the TSM registers. After a hardware

RESET signal, or executing a software RESET instruction, the TSM register is reset to

$FFFFFFFF; that value enables all 32 slots for data transmission. The transmit DC setting

determines how many of these control bits is actually used.

12.8.15 Receive Slot Mask Registers (RSMA, RSMB)

The Receive Slot Mask Registers are two 16-bit read/write registers. In the Network mode, these

registers are used by the receiver to determine which action to take in the current time slot.

Depending on the setting of the bits, the receiver either ignores the receiver data signal(s), or

receives a data word, generating the appropriate receive status.

RSMA and RSMB can be viewed as one 32-bit register, RSM. Bit n in RSM (RSMn) is an

enable/disable control bit for time slot N.

Figure 12-31. Receive Slot Mask Register (RSMA)

See Programmer’s Sheet on Appendix page B - 83

Figure 12-32. Receive Slot Mask Register (RSMB)

See Programmer’s Sheet on Appendix page B - 83

Base + $E

Read

RSMA [15:0]

Write

Reset

Base + $F

Read

RSMB [31:16]

Write

Reset

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