DSP56857 datasheet(362/662 Pages) FREESCALE

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Resets

5685X Digital Signal Controller User Manual, Rev. 4

12-62

Freescale Semiconductor

12.11 Resets

The ESSI is affected by Power-On Reset (POR) and ESSI reset.

POR is generated by asserting either the Reset pin or the (COP) timer reset. The POR initializes

all control registers and clears the ESSIEN bit in SCR2 and disables the ESSI.

The ESSI reset is generated when the ESSIEN bit in the SCR2 is cleared. The ESSI status bits are

preset to the same state produced by the POR. The ESSI control bits are unaffected. The ESSI

reset is useful for selective reset of the ESSI without changing the present ESSI control bits and

without affecting the other peripherals.

The correct sequence to initialize the ESSI is as follows:

1. Issue a Power-On or ESSI Reset.

2. Program the ESSI Control Registers.

3. Set the ESSIEN bit in SCR2.

4. Write data to the STX register(s).

5. Enable transmit and receive operations.

This procedure ensures proper operation of the ESSI by using the Power-On Reset (POR) or

ESSI reset before changing any of the control bits listed in Table 12-26. These control bits

should not be changed during ESSI operation.

Note:

The ESSI bit clock must go low for at least one complete period to ensure proper ESSI

reset.

Table 12-26.

ESSI Control Bits Requiring

Reset Before Change

Control Register

Bit

SRXCR

STXCR

PSR

WL[1:0]

DC[4:0]

PM[7:0]

SCR2

TEFS

TFSL

TFSI

NET

TSCKP

TSHFD

SYN

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