DSP56857 datasheet(360/662 Pages) FREESCALE

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Clock Operation Description

5685X Digital Signal Controller User Manual, Rev. 4

12-60

Freescale Semiconductor

Figure 12-34. ESSI Clock Generation

12.10 Clock Operation Description

12.10.1 ESSI Clock and Frame Sync Generation

Data clock and frame sync signals can be generated internally by the ESSI or can be obtained

from external sources. If internally generated, the ESSI clock generator is used to derive bit clock

and frame sync signals from the peripheral clock. The ESSI clock generator consists of a

selectable, fixed prescaler and a programmable prescaler for bit rate clock generation. A

programmable frame rate divider and a word length divider are used for frame rate sync signal

generation.

Table 12-25.

Clock Summary

Clock

Source

Characteristics

SCK

Internal/

External

Transmit data is changed on the rising edge of this clock. The RSCKP bit of the SCR2

SC0

Internal/

External

Receive data is captured on the falling edge of this clock. The RSCKP bit of the SCR3

SC2

Internal/

External

Transmit frames begin with the rising edge of this signal. See the definition of the

TEFS bit of the SCR2 register for timing options. The TFSI bit can invert this signal if

required.

SC1

Internal/

External

Receive frames begin with the rising edge of this signal. See the definition of the

REFS bit of the SCR3 register for timing options.

(SC2, SC1)

Serial Bit Clock

Word Divider

(/8, /10, /12, /16)

Word clock

Frame Divider

(/1 to /32)

Frame clock

(SCK, SC0)

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