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DSP56857 Datasheet(PDF) 361 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 361 Page - Freescale Semiconductor, Inc |
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361 / 662 page  Clock Operation Description Enhanced Synchronous Serial Interface (ESSI), Rev. 4 Freescale Semiconductor 12-61 Figure 12-35. ESSI Transmit Clock Generator Block Diagram Figure 12-36 demonstrates the frame sync generator block for the transmit section. When internally generated, both receive and transmit frame sync are generated from the word clock and are defined by the frame rate Divider (DC) field bits and the Word Length (WL) field bits of the ESSI Transmit Data Control Register (STXCR). The receive section contains an equivalent circuit for its frame sync generator. Figure 12-36. ESSI Transmit Frame Sync Generator Block Diagram /2 IP_CLK Prescaler (/1 or /8) Divider (/1 to /256) /2 SCKD (1=output) SCKD (0=input) Serial Bit Clock SCKD (1=output) Word Length Divider Word Clock WL[1:0] PSR PM[7:0] /4 DIV4DIS FIX_CLK SCK Frame Rate DC[4:0] Frame Sync TFSL Tx Control TFSI TFSI Tx Frame Sync Out Tx Frame Sync In Word Clock SC2 |
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