DSP56857 datasheet(436/662 Pages) FREESCALE

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DSC Side Registers

5685X Digital Signal Controller User Manual, Rev. 4

16-10

Freescale Semiconductor

16.8 DSC Side Registers

The DSC core views the HI8 as a memory mapped peripheral occupying four 16-bit words in

data memory space. The DSC can use the HI8 as a normal memory mapped peripheral, using

either standard polled or interrupt programming techniques. Separate transmit and receive data

registers are double-buffered to allow the DSC and Host Processor to efficiently transfer data at

high speed. Memory mapping allows DSC core communication with the HI8 registers to be

accomplished using standard instructions and addressing modes. In addition, the MOVE

instruction allows HI8-to-memory and memory-to-HI8 data transfers without going through an

intermediate register. Both hardware and software reset disable the HI8. These registers can be

accessed by the DSC core, or by the external host.

16.8.1 HI8 Control Register (HCR)

The HI8 Control Register (HCR) is 16-bit read/write Control register used by the DSC core to

control the HI8 operating mode. Reserved bits are read and written as 0, ensuring future

compatibility. Figure 16-4 illustrates the programming model of the HCR. The initialization

values for the HCR bits are described in Table 16-6. The HCR bits are described in the following

paragraphs.

Figure 16-4. Host Control Register (HCR)

See Programmer’s Sheet on Appendix page B - 137

16.8.1.1 Reserved Bits—Bits 15–9

These bits are reserved or not implemented. They are read as, and written with 0s.

16.8.1.2 Host Request Mode Select (HRMS)—Bit 8

The Host mode Select (HRMS) bit controls the host request pins. Table 16-4 shows the

functionality of the I/O pins controlled by this bit.

Note:

The direction of the HACK / HRRQ pin changes based on the HRMS setting. HACK

is an input, while HRRQ is an output.

Base + $0

Read

HRMS HDDS

TDMAEN

RDMAEN

HF3

HF2

HCIE

HTIE

HRIE

Write

Reset

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