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DSP56857 Datasheet(PDF) 437 Page - Freescale Semiconductor, Inc

Part # DSP56857
Description  Digitial Signal Controller
PDF  662 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 437 Page - Freescale Semiconductor, Inc

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DSC Side Registers
Host Interface Eight (HI8), Rev. 4
Freescale Semiconductor
16-11
16.8.1.3 Host Dual Data Strobe (HDDS)—Bit 7
When the Host Dual Data Strobe (HDDS) bit is set, the HI8 operates in the Dual Data Strobe Bus
mode; a host bus with separated read and write data strobes. When the HDDS bit is cleared, the
HI8 operates in the Single Strobe Bus mode, i.e. a Host bus with a single Data Strobe signal.
Please see Figure 16-5 for a description of the two types of buses. The HDDS bit is cleared on
hardware reset.
Figure 16-5. Single and Dual Data Strobe Bus Modes
Table 16-4.
HRMS Configuration of HREQ and HACK Pins
Pin
HRMS = 0
HRMS = 1
HREQ / HTRQ
HREQ
HTRQ
HACK / HRRQ
HACK
HRRQ
Single Data Strobe Mode (HDDS = 0)
HRW
HDS
In Single Strobe Bus mode, a DS (Data-Strobe) signal qualifies the access, while a R/W
(Read-Write) signal specifies the direction of it.
Host Data
Dual Data Strobe Mode (HDDS = 1)
HWR
HRD
Write cycle
Read cycle
In Dual Strobe Bus mode, there are special RD and WR signals that both qualify the
access as being a read or a write access, respectively.
HCS
HCS



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