DSP56857 datasheet(440/662 Pages) FREESCALE

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DSC Side Registers

5685X Digital Signal Controller User Manual, Rev. 4

16-14

Freescale Semiconductor

Note:

This bit is always 0 if HRMS = 1 since the HREQ and HACK function is disabled and

Host DMA operations are disabled.

16.8.2.3 Host Flags 0 and 1 (HF0–HF1)—Bits 4–3

The Host Flag 0-1 (HF0 and HF1) bits are used as a general purpose flags for Host-to-DSC

communication. The HF0 and HF1 bits can be set or cleared by the Host. These bits reflect the

status of Host Flags HF0 and HF1 in the Interface Control Register (ICR) on the Host Side.

These two flags are not designated for any specific purpose, but are considered general purpose

flags. They can be used individually or as encoded pairs in a simple Host-to-DSC communication

protocol, implemented in both the DSC and the Host Processor software. The HF0 and HF1 bits

are cleared on hardware reset.

16.8.2.4 Host Command Pending (HCP)—Bit 2

The Host Command Pending (HCP) flag bit reflects the status of the HC bit in the Command

Vector Register (CVR), indicating a Host Command Interrupt is pending. The HCP bit is set

when the HC bit is set, and both bits are cleared by the HI8 hardware when the interrupt request is

serviced by the DSC core. The Host can also clear the HC bit, thereby clearing the HCP bit as

well. The HCP bit is cleared on hardware reset.

16.8.2.5 Host Transmit Data Empty (HTDE)—Bit 1

The Host Transmit Data Empty (HTDE) flag bit indicates the Host Transmit Data (HTX) register

is empty and can be written by the DSC core. The HTDE bit is set when the HTX register is

transferred to the RXH/RXL registers, and cleared when Host Transfer Date (HTX) is written by

the DSC core. When the HTDE bit is set, the HI8 generates a Transmit Data Full DMA request.

HTDE can also be set by the Host Processor using the initialize function. The HTDE bit is set on

hardware reset.

16.8.2.6 Host Receive Data Full (HRDF)—Bit 0

The Host Receive Data Full (HRDF) flag bit indicates the Host Receive Data (HRX) register

contains data from the Host Processor. The HRDF bit is set when data is transferred from the

TXH/TXL registers to the Host Receive Data (HRX) register. The HRDF bit is cleared when the

HRX register is read by the DSC core. When the HRDF bit is set, the HI8 generates a receive

data full DMA request. The HRDF bit can also be cleared by the Host Processor using the

initialize function. The HRDF bit is cleared on hardware reset.

DSP56857 Datasheet(PDF) 440 Page - Freescale Semiconductor, Inc