DSP56857 datasheet(442/662 Pages) FREESCALE

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DSC Side Registers

5685X Digital Signal Controller User Manual, Rev. 4

16-16

Freescale Semiconductor

16.8.6 HI8 DSC Core Interrupts

The HI8 may request interrupt service from either the DSC core or the Host Processor. The DSC

core interrupts are internal and do not require the use of an external interrupt pin. Please refer to

Figure 16-9. When the appropriate interrupt enable bit in the Host Control Register (HCR) is set,

an interrupt condition caused by the Host Processor sets the appropriate bit in the Host Status

acknowledges interrupts caused by the Host Processor by jumping to the appropriate interrupt

service routine. The three possible interrupts are:

•

Receive Data Register Full

•

Transmit Data Register Empty

•

Host Command

The Host Command can access any interrupt vector in the Interrupt Vector Table, although it has

a set of vectors reserved for Host Command use. The DSC interrupt service routine must read or

write the appropriate HI8 register. For example, clear the HRDF or HTDE bit to clear the

interrupt. In the case of Host Command Interrupts, the interrupt acknowledge from the DSC core

Program Controller Unit (PCU) clears the pending interrupt condition.

Table 16-6.

DSC Side Registers After Reset

Name

Data

Reset Type

Hardware

Rest1

Software

Reset2

STOP

Reset3

HSR

HDMA

—

HF1-HF0

—

HCP

HTDE

HRDF

HRX

HRX[15:0]

Empty

HTX

HTX[15:0]

Empty

1. Caused by RESET signal

2. Caused by executing the RESET instruction

3. Caused by executing the STOP instruction

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