DSP56857 datasheet(446/662 Pages) FREESCALE

446 / 662 page

Host Side Registers

5685X Digital Signal Controller User Manual, Rev. 4

16-20

Freescale Semiconductor

Host DMA controller. The DMA Control bits HM0 and HM1 select the size of the DMA word to

be transferred as shown inTable 16-9. The direction of the DMA transfer is selected by the

TREQ and RREQ bits.

When both HM1 and HM0 are cleared, the Host DMA mode is disabled and the TREQ and

RREQ control bits are used for the Host Processor interrupting via the external Host Request

HREQ output pin when the HRMS bit is also cleared. In the Interrupt mode, the Host

Acknowledge HACK input pin is used for the MC68000 family vectored Interrupt Acknowledge

input.

When HM1 is set, the Host DMA mode is enabled and the Host Request (HREQ) pin is not

available for Host Processor interrupts. When the Host DMA mode is enabled, the TREQ and

RREQ bits select the direction of Host DMA transfers; the Host Acknowledge (HACK) input pin

is used as a Host DMA transfer acknowledge input.

When the Host DMA direction is from DSC-to-Host, the contents of the selected register, RXH

or RXL, are enabled onto the Host data bus when the HACK pin is asserted.

If the Host DMA direction is from Host-to-DSC, the contents of the selected register are enabled

onto the Host data bus when the HACK pin is asserted.

If the Host DMA direction is from Host-to-DSC, the selected register is written to TXH or TXL

from the Host data bus when the HACK pin is asserted.

The size of the Host DMA word to be transferred is determined by the Host mode 0 (HM0) bit.

The HI8 register selected during a Host DMA transfer is determined by a 2-bit address counter,

preloaded with the value in HM1 and HM0. The address counter substitutes for the Host Address

inputs, HA1 and HA0 during a Host DMA transfer. The Host Address input HA2 is forced to 1

during each Host DMA transfer. The address counter can be initialized when the INIT bit is set.

After each DMA transfer, the address counter is incriminated to the next register.

Table 16-9.

Mode (HM1, HM0) Bit Definition (HRMS = 0)

HM1

HM0

Mode

Interrupt mode (HDMA off)

Illegal

HDMA mode; 16-bit

HDMA mode; 8-bit

DSP56857 Datasheet(PDF) 446 Page - Freescale Semiconductor, Inc