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DSP56857 Datasheet(PDF) 448 Page - Freescale Semiconductor, Inc

Part # DSP56857
Description  Digitial Signal Controller
PDF  662 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 448 Page - Freescale Semiconductor, Inc

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Host Side Registers
5685X Digital Signal Controller User Manual, Rev. 4
16-22
Freescale Semiconductor
16.9.1.6 ICR Transmit Request Enable (TREQ)—Bit 1
The Transmit Request Enable (TREQ) bit is used to control the HREQ pin for Host transmit data
transfers. In the Interrupt mode, and the DMA is off, TREQ is used to enable interrupt requests
via the external Host Request (HREQ or HTRQ) pin when the Transmit Data Register Empty
(TXDE) status bit in the Interrupt Status Register (ISR) is set. When TREQ is cleared, TXDE
interrupt is disabled. When TREQ is set, the external Host Request HREQ or HTRQ pin is
asserted if TXDE is set in the Interrupt mode.
In DMA modes, the TREQ must be set or cleared by software to select the direction of DMA
transfers. Setting TREQ sets the direction of the DMA transfer to be from Host-to-DSC and
enables the HREQ pin to request these data transfers.
16.9.1.7 Receive Request Enable (RREQ)—Bit 0
This bit is used to control the HREQ pin for Host receive data transfers. In the Interrupt mode
(HDMA off), the RREQ is used to enable interrupt requests via the external Host Request (HREQ
or HRRQ) pin when the Receive Data Register Full (RXDF) status bit in the Interrupt Status
register (ISR) is set. When RREQ is cleared, RXDF interrupts are disabled. When RREQ is set,
the external Host Request HREQ pin or HRRQ is asserted if RXDF is set in interrupt mode.
In HDMA modes, the RREQ bit must be set or cleared by software to select the direction of
DMA transfers. Setting the RREQ bit sets the direction of the HDMA transfer to be from the
DSC-to-Host, enabling the HREQ pin to request these data transfers. RREQ is cleared by DSC
reset.
Table 16-10,Table 16-11, and Table 16-12 summarizes the effect of RREQ and TREQ on the
HREQ/HTRQ and HACK/HRRQ pins. TREQ is cleared by DSC reset.
Table 16-10.
HREQ Pin Definition–Interrupt Mode (HRMS = 0, HM1 = HM0 = 0)
TREQ
RREQ
HREQ Pin
0
0
No interrupts (Polling)
0
1
RXDF Request (Interrupt)
1
0
TXDE Request (Interrupt)
1
1
RXDF and TXDE Request (Interrupt)



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