DSP56857 datasheet(444/662 Pages) FREESCALE

444 / 662 page

Host Side Registers

5685X Digital Signal Controller User Manual, Rev. 4

16-18

Freescale Semiconductor

Standard Host Processor instructions such as byte move and addressing modes are used to

communicate with the HI8 registers. The HI8 registers are addressed allowing 8-bit Host

Processors to use 8/16-bit load and store instructions for data transfers. The HREQ / HTRQ and

HACK / HRRQ handshake flags are provided for polled or interrupt driven data transfers with the

Host Processor. Because the DSC interrupt response is sufficiently rapid, most host

microprocessors can load or store data at their maximum programmed I/O instruction rate

without testing the handshake flags for each transfer. If full handshake is not required, the Host

Processor can treat the DSC as a fast device, allowing data to be transferred between the Host

Processor and the DSC at the fastest host processor data rate.

One of the most innovative features of the HI8 is the Host Command feature. With this feature,

the Host Processor can issue vectored interrupt requests to the DSC core. The Host can select any

of 128 DSC interrupt routines to be executed by writing a vector address register in the HI8. This

flexibility allows the Host programmer to execute as many as 128 pre-programmed functions

inside the DSC core. For example, Host Interrupts permits the Host Processor to read or write

DSC registers (data or program memory locations), force interrupt handlers (i.e., ESSI, SCI,

IRQA and IRQB interrupt routines) to perform control and debugging operations when interrupt

routines are implemented in the DSC to perform these tasks.

Note:

Please be aware when the DSC core enters the Stop mode, the HI8 pins are electrically

disconnected internally, thus disabling the HI8 until the core leaves Stop mode. While

the HI8 configuration remains unchanged in Stop mode, the core cannot be restarted

via the HI8 interface.

Do not issue a STOP command to the DSC via the HI8 unless some other mechanism

for exiting Stop mode is provided.

16.9.1 Interface Control Register (ICR)

The Interface Control Register (ICR) is an 8-bit read/write control register used by the Host

Processor to control the HI8 interrupts and flags. The ICR cannot be accessed by the DSC core,

but it allows the use of bit manipulation instructions on the Control register. The control bits are

described in the following paragraphs. Figure 16-10 illustrates the programming model of the

ICR.

Figure 16-10. Interface Control Register (ICR)

See Programmer’s Sheet on Appendix page B - 141

Base + $0

Read

INIT

HM1

HM0

HF1

HF0

HLEND

TREQ

RREQ

Write

Reset

0000

DSP56857 Datasheet(PDF) 444 Page - Freescale Semiconductor, Inc

DSP56857 Datasheet(HTML) 444 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL