DSP56857 datasheet(443/662 Pages) FREESCALE

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Host Side Registers

Host Interface Eight (HI8), Rev. 4

Freescale Semiconductor

16-17

Figure 16-9. HSR–HCR Operation

16.9 Host Side Registers

The HI8 appears to the Host Processor as 8-byte-wide registers. The Host can access the HI8

asynchronously by using polling techniques or interrupt-based techniques. Separate transmit and

receive data registers are double buffered to allow the DSC core and Host Processor to transfer

data efficiently at High speed.

The HI8 appears to the Host Processor as a memory mapped peripheral occupying eight bytes in

the Host Processor address space, detailed in Figure 16-7. These registers can be viewed as:

•

Interface Control Register (ICR)

•

Interface Status Register (ISR)

•

Two data registers

— Receive Data High/Low (RXH/RXL)

— Transmit Data High/Low (TXH/TXL)

•

Two vector registers

— Interface Vector Receive (IVR)

— Command Vector Register (CVR)

The CVR is a special command register used by the Host Processor to issue commands to the

DSC. Each of these registers can be accessed only by the Host Processor.

HCR

Status

Enable

DSC Core Interrupts

Receive Data Full

Transmit Data Empty

Host Command

HRIE

HTIE

HCIE

HF2

HF3

HSR

HF1

HF0

HCP HTDE HRDF

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