DSP56857 datasheet(447/662 Pages) FREESCALE

447 / 662 page

Host Side Registers

Host Interface Eight (HI8), Rev. 4

Freescale Semiconductor

16-21

When the address counter reaches the highest register (RXL or TXL), the address counter is not

incriminated but is loaded with the value in HM1 and HM0. This allows 8- or 16-bit data to be

transferred in a circular fashion and eliminates the need for the DMA controller to supply the

Host Address HA2, HA1, and HA0 pins. For 16-bit data transfers, the DSC interrupt rate is

reduced by a factor of two from the Host Request rate.

HM1 and HM0 are cleared by DSC reset.

Note:

When operating in 8-bit HDMA mode, the HLEND affects the location (upper or

lower byte) of the 8-bit value in the DSC register (HRX/HTX). For example, in

Host-to-DSC transfers, if HLEND = 0 the transferred data is placed in the lower half of

the HRX register. If HLEND = 1 the data would appear in the upper half of the

Note:

Prior to initiating an 8-bit Host-to-DSC transfer the Host should ensure the TXH/TXL

registers at address 6 is initialized to 0 because the contents of this register are

transferred with the TXL/TXH register to the HRX register.

16.9.1.3 Host Flag 1 (HF1)—Bit 4

The Host Flag 1 (HF1) bit is used as a general purpose flag for Host-to-DSC communication. The

HF1 bit can be set or cleared by the Host Processor, but cannot be changed by the DSC core. The

HF1 bit is reflected in the HSR on the DSC Side. The HF1 bit is cleared on DSC reset.

16.9.1.4 Host Flag 0 (HF0)—Bit 3

The Host Flag 0 (HF0) bit is used as a general purpose flag for Host-to-DSC communication. The

HF0 bit can be set or cleared by the Host Processor, but cannot be changed by the DSC core. The

HF0 bit is reflected in the HSR on the DSC Side. The HF0 bit is cleared on DSC reset.

16.9.1.5 ICR Host Little Endian (HLEND)—Bit 2

The Host Little Endian (HLEND) bit allows the HI8 to be accessed by the Host in Little Endian

or Big Endian data order. When the HLEND bit is set, the HI8 can be accessed by the Host in

Little Endian order. The RXH/TXH is located at address $7 and RXL/TXL at $6. When the

HLEND bit is cleared, the HI8 can be accessed by the Host in Big Endian Host data order. The

RXH/TXH is located at address $6 and RXL/TXL at $7. The HLEND bit is cleared on hardware

reset.

DSP56857 Datasheet(PDF) 447 Page - Freescale Semiconductor, Inc