DSP56857 datasheet(449/662 Pages) FREESCALE

449 / 662 page

Host Side Registers

Host Interface Eight (HI8), Rev. 4

Freescale Semiconductor

16-23

16.9.2 Command Vector Register (CVR)

The Command Vector Register (CVR) is used by the Host Processor, causing the DSC core to

execute an interrupt. The Host Command feature is independent of any of the data transfer

mechanisms in the HI8. The Host Interface can execute any of the 128 possible interrupt requests

to the DSC core. Please refer to the Interrupt Controller (ITCN) chapter for further details.

Figure 16-11. Command Vector Register (CVR)

See Programmer’s Sheet on Appendix page B - 142

16.9.2.1 Host Command (HC)—Bit 7

This bit is used by the Host Processor to handshake the execution of Host Command interrupts.

Normally, the Host Processor sets HC = 1 to request the Host Command interrupt from the DSC

core. When the Host Command interrupt is acknowledged by the DSC core the HC bit is cleared

by the HI8 hardware. The Host Processor can read the state of the HC bit to determine when the

Host Command has been accepted. After writing HC = 1 to the CVR, the Host must not write to

the CVR again until the HC bit is cleared by the HI8 hardware. Setting the HC bit causes Host

Command pending to be set in the Host Status Register.

Table 16-11.

HREQ Pin Definition–Host Mode (HRMS = 0, HM1, HM0 Set for DMA)

TREQ

RREQ

RREQ Pin

DMA Transfers Disabled

DSC–> Host Request (RX)

Host–> DSC Request (TX)

Undefined (illegal)

Table 16-12.

HTRQ and HRRQ Interrupt Mode (HRMS = 1)

TREQ

RREQ

HTRQ Pin

HRRQ Pin

No Interrupts (Polling)

RXDF Request (Interrupt)

TXDE Request (Interrupt)

No Interrupt (Polling)

TXDE Request (Interrupt)

RXDF Request (Interrupt)

Base + $1

Read

HV6

HV5

HV4

HV3

HV2

HV1

HV0

Write

Reset

00000

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