DSP56857 datasheet(450/662 Pages) FREESCALE

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Servicing the Host Interface

5685X Digital Signal Controller User Manual, Rev. 4

16-24

Freescale Semiconductor

16.9.2.2 CVR Host Vector (HV)—Bits 6–0

These seven bits select the Host Command interrupt offset address in the vector table to be used

by the Host Command interrupt logic. When the Host Command interrupt is recognized by the

DSC interrupt control logic the offset address of the interrupt vector table taken is 2

× HVI0, 6.

The Host can write HC and HV in the same write cycle.

The Host Processor can select any of the 128 possible offset addresses of the interrupt vector

table in the DSC by writing this address divided by 2, and equal to the vector number, into HV

bits. This means the Host Processor can force any of the existing interrupt handlers, SW

interrupts such as ESSI, SCI, IRQA, or IRQB and can use any of the reserved or otherwise

unused interrupt vectors.

16.10 Servicing the Host Interface

The HI8 can be serviced by using one of the following protocols:

•

Polling

•

Interrupts

•

Host DMA

From the Host Processor viewpoint, the service consists of making a data transfer because this is

the only way to reset the appropriate status bits.

16.10.1 Interface Status Register (ISR)

The Interface Status Register (ISR) is an 8-bit read-only status register used by the Host

Processor to interrogate the status and flags of the HI8. The Host Processor can write this address

without affecting the internal state of the HI8, useful to access all of the HI8 registers by stepping

through the HI8 addresses. The ISR can not be accessed by the DSC core. The status bits are

described in the following paragraphs.

Figure 16-12. Interface Status Register (ISR)

See Programmer’s Sheet on Appendix page B - 143

Base + $2

Read

HREQ

DMA

HF3

HF2

TRDY

TXDE RXDF

Write

Reset

0000

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