DSP56857 datasheet(452/662 Pages) FREESCALE

452 / 662 page

Servicing the Host Interface

5685X Digital Signal Controller User Manual, Rev. 4

16-26

Freescale Semiconductor

16.10.1.5 Host Flag 2 (HF2)—Bit 3

The Host Flag 2 (HF2) bit in the Interface Control Register (ISR) indicates the state of Host Flag

2 in the Host Control Register on the DSCDSC Side. The HF2 bit can only be changed by the

DSC Side. Please see Figure 16-4.

16.10.1.6 Transmitter Ready (TRDY)—Bit 2

The Transmitter Ready (TRDY) flag bit indicates TXH, TXL, and the HRX registers are empty.

When the TRDY bit is set, the data the Host Processor writes to the TXH and TXL registers is

immediately transferred to the DSC Side of the HI8. The many applications can use this feature.

For example, if the Host Processor issues a Host Command causing the DSC core to read the

HRX, the Host Processor can be guaranteed the data transferred to the HI8 is being received by

the DSC core.

16.10.1.7 Transmit Data Register Empty (TXDE)—Bit 1

Setting the Transmit Data Register Empty (TXDE) bit indicates the transmit byte registers (TXH,

and TXL) are empty and can be written by the Host Processor. TXDE is set when the transmit

byte registers are transferred to the HRX register. TXDE is cleared when the transmit TXL/TXH

Processor. TXDE can be set by the Host Processor using the initialize feature. TXDE may be

used to assert the external HREQ pin if the TREQ bit is set. Regardless of whether the TXDE

interrupt is enabled, TXDE provides valid status so polling techniques may be used by the Host

Processor.

16.10.1.8 Receive Data Register Full (RXDF)—Bit 0

Setting the Receive Data Register Full (RXDF) flag bit indicates the receive byte registers (RXH

and RXL) contain data from the DSC Side and can be read by the Host Processor. The RXDF bit

is set when the HTX is transferred to the receive byte registers. RXDF is cleared when the receive

data RXL/RXH (based on HLEND setting, the one at address offset seven) is read by the Host

Processor. RXDF can be used to assert the external HREQ pin if the RREQ bit is set. Regardless

of whether the RXDF interrupt is enabled, RXDF provides valid status so polling techniques may

be used by the Host Processor.

16.10.2 Interrupt Vector Register (IVR)

The Interrupt Vector Register (IVR) is an 8-bit read/write register typically containing the

interrupt vector number used with MC68000 family processor vectored interrupts. Only the Host

Processor can read and write this register. The contents of IVR are placed on the Host data bus

(H0–H7) when both HREQ and HACK pins are asserted and Host DMA is not enabled. The

DSP56857 Datasheet(PDF) 452 Page - Freescale Semiconductor, Inc