DSP56857 datasheet(456/662 Pages) FREESCALE

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Servicing the Host Interface

5685X Digital Signal Controller User Manual, Rev. 4

16-30

Freescale Semiconductor

16.10.6 HI8 Host Processor Data Transfer

The HI8 looks like static RAM to the Host Processor. To transfer data with the HI8, the Host

Processor must:

•

Assert the HI8 address to select the register to be read or written

•

Select the direction of the data transfer

•

Strobe the data transfer

16.10.7 Polling

In the polling mode of operation, the HREQ pin is not connected to the Host Processor and

HACK must be negated, ensuring the IVR data is not being driven on H0–H7 when other

registers are being polled. HACK can also be configured as a GPIO pin if the HACK function is

not required.

Figure 16-18 illustrates the Host Processor first performs a data read transfer to read the ISR to

determine, whether:

•

RXDF = 1 indicates the Receive Data register is full, and a data read should be performed.

•

TXDE = 1 indicates the Transmit Data register is empty, and a data write can be

performed.

•

When HREQ = 1, the HREQ pin has been asserted, and one of the previous two conditions

exist.

Generally, after the appropriate data transfer has been made, the corresponding status bit is

updated to reflect the transfer.

If the Host Processor has issued a command to the DSC by writing to the CVR and setting the HC

bit, it can read the HC bit in the CVR to determine when the command has been accepted by the

interrupt controller in the DSC core. When the command has been accepted for execution, the HC

bit is cleared by the interrupt controller in the DSC core.and/or RXDF = 1 and the corresponding

enable bit (TREQ or RREQ, respectively) are set. This procedure is depicted in Figure 16-18.

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